Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E
Rev. B | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
1
RE
2
DE
3
DI
4
V
CC
8
B
7
A
6
GND
5
ADN4690E/
ADN4694E
TOP VIEW
(Not to Scale)
10471-002
Figure 3. ADN4690E/ADN4694E Pin Configuration
DNC
1
2
3
4
V
CC
14
13
12
11
5
10
GND
6
Y
9
GND
7
DNC
8
NOTES
1. DNC = DO NOT CONNECT.
ADN4692E/
ADN4695E
TOP VIEW
(Not to Scale)
RO
RE
DE
DI
V
CC
A
B
Z
10471-104
Figure 4. ADN4692E/ADN4695E Pin Configuration
Table 8. Pin Function Descriptions
ADN4690E/
ADN4694E
Pin No.
1
ADN4692E/
ADN4695E
P
in No.
1
Mnemonic Description
1 2 RO Receiver Output. Type 1 receiver (ADN4690E/ADN4692E), when enabled:
If A − B ≥ 50 mV, then RO = logic high. If A − B ≤ −50 mV, then RO = logic low.
Type 2 receiver (ADN4694E/ADN4695E), when enabled:
If A − B ≥ 150 mV, then RO = logic high. If A − B ≤ 50 mV, then RO = logic low.
Receiver output is undefined outside these conditions.
2 3
RE
Receiver Output Enable. A logic low on this pin enables the receiver output, RO.
A logic high on this pin places RO in a high impedance state.
3 4 DE Driver Output Enable. A logic high on this pin enables the driver differential outputs.
A logic low on this pin places the driver differential outputs in a high impedance state.
4 5 DI Driver Input. Half-duplex (ADN4690E/ADN4694E), when enabled:
A logic low on DI forces A low and B high, whereas a logic high on DI forces A high and B low.
Full-duplex (ADN4692E/ADN4695E), when enabled:
A logic low on DI forces Y low and Z high, whereas a logic high on DI forces Y high and Z low.
5 6, 7 GND Ground.
N/A 9 Y Noninverting Driver Output Y.
N/A 10 Z Inverting Driver Output Z.
6 N/A A Noninverting Receiver Input A and Noninverting Driver Output A.
N/A 12 A Noninverting Receiver Input A.
7 N/A B Inverting Receiver Input B and Inverting Driver Output B.
N/A 11 B Inverting Receiver Input B.
8 13, 14 V
Power Supply (3.3 V ± 0.3 V).
N/A 1, 8 DNC Do Not Connect. Do not connect to these pins.
1
N/A means not applicable.
