Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E
Rev. B | Page 5 of 20
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output
V
A
(V) V
B
(V) V
ID
(V) V
IC
(V) RO
2.4 0 2.4 1.2 H
0 2.4 −2.4 1.2 L
3.475 3.325 0.15 3.4 H
3.425 3.375 0.05 3.4 L
−0.925 −1.075 0.15 −1 H
−0.975 −1.025 0.05 −1 L
TIMING SPECIFICATIONS
V
CC
= 3.0 V to 3.6 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 100 Mbps
Propagation Delay t
PLH
, t
PHL
2 2.5 3.5 ns See Figure 23, Figure 26
Differential Output Rise/Fall Time t
R
, t
F
2 2.6 3.2 ns See Figure 23, Figure 26
Pulse Skew |t
PHL
− t
PLH
| t
SK
30 150 ps See Figure 23, Figure 26
Part-to-Part Skew t
SK(PP)
0.9 ns See Figure 23, Figure 26
Period Jitter, rms (One Standard Deviation)
2
t
J(PER)
2 3 ps 50 MHz clock input
3
(see Figure 25)
Peak-to-Peak Jitter
2, 4
t
J(PP)
150 ps 100 Mbps 2
15
− 1 PRBS input
5
(see Figure 28)
Disable Time from High Level t
PHZ
4 7 ns See Figure 24, Figure 27
Disable Time from Low Level t
PLZ
4 7 ns See Figure 24, Figure 27
Enable Time to High Level t
PZH
4 7 ns See Figure 24, Figure 27
Enable Time to Low Level t
PZL
4 7 ns See Figure 24, Figure 27
RECEIVER
Propagation Delay t
RPLH
, t
RPHL
2 6 ns C
L
= 15 pF (see Figure 29, Figure 32)
Rise/Fall Time t
R
, t
F
1 2.3 ns C
L
= 15 pF (see Figure 29, Figure 32)
Pulse Skew |t
RPHL
– t
RPLH
| C
L
= 15 pF (see Figure 29, Figure 32)
Type 1 Receiver (ADN4690E, ADN4692E) t
SK
100 300 ps
Type 2 Receiver (ADN4694E, ADN4695E) t
SK
300 500 ps
Part-to-Part Skew
6
t
SK(PP)
1 ns C
L
= 15 pF (see Figure 29, Figure 32)
Period Jitter, RMS (One Standard Deviation)
2
t
J(PER)
4 7 ps 50 MHz clock input
3
(see Figure 31)
Peak-to-Peak Jitter
2, 4
100 Mbps 2
15
− 1 PRBS input
5
(see Figure 34)
Type 1 Receiver (ADN4690E, ADN4692E) t
J(PP)
200 700 ps
Type 2 Receiver (ADN4694E, ADN4695E) t
J(PP)
225 800 ps
Disable Time from High Level t
RPHZ
6 10 ns See Figure 30, Figure 33
Disable Time from Low Level t
RPLZ
6 10 ns See Figure 30, Figure 33
Enable Time to High Level t
RPZH
10 15 ns See Figure 30, Figure 33
Enable Time to Low Level t
RPZL
10 15 ns See Figure 30, Figure 33
1
All typical values are given for V
CC
= 3.3 V and T
A
= 25°C.
2
Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
3
t
R
= t
F
= 0.5 ns (10% to 90%), measured over 30,000 samples.
4
Peak-to-peak jitter specifications include jitter due to pulse skew (t
SK
).
5
t
R
= t
F
= 0.5 ns (10% to 90%), measured over 100,000 samples.
6
HP4194A impedance analyzer or equivalent.
