ADV7401
Rev. B | Page 12 of 20
TIMING DIAGRAMS
05340-003
SDA1/SDA2
SCLK1/SCLK2
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
t
3
Figure 3. I
2
C Timing
05340-004
LLC1
P2–P9, P12–P19,
P22–P29, VS, HS,
FIELD/DE,
SFL/SYNC_OUT
t
9
t
10
t
12
t
11
Figure 4. Pixel Port and Control SDR Output Timing (SD Core)
05340-005
t
9
LLC1
P2–P9, P12–P19,
P22–P29
t
13
t
14
t
10
Figure 5. Pixel Port and Control SDR Output Timing (CP Core)
LLC1
P6–P9,
P12–P19
t
16
t
18
t
15
t
17
05340-006
Figure 6. Pixel Port and Control DDR Output Timing (CP Core)
t
9
t
10
t
20
t
19
DCLK_IN
DE_IN
HS_IN
VS_IN
CONTROL
INPUTS
05340-008
P0–P1, P10–P11,
P20–P21, P22–P29,
P31–P32, P33–P40
Figure 7. Digital Input Port and Control Input Timing
ADV7401
Rev. B | Page 13 of 20
DETAILED FUNCTIONALITY
ANALOG FRONT END
Four high quality 10-bit ADCs enable true 8-bit video
decoder
12 analog input channel mux enables multisource
connection without the requirement of an external mux
Four current and voltage clamp control loops ensure any
dc offsets are removed from the video signal
SCART functionality and SD RGB overlay on CVBS
controlled by fast blank input
Four internal antialias filters to remove out-of-band noise
on standard definition input video signals
SDP PIXEL DATA OUTPUT MODES
8-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD
16-bit YCrCb with embedded time codes and/or HS, VS,
and FIELD
24-bit YCrCb with embedded time codes and/or HS, VS,
and FIELD
CP PIXEL DATA OUTPUT MODES
Single data rate (SDR) 8-bit 4:2:2 YCrCb for 525i, 625i
Single data rate (SDR) 16-bit 4:2:2 YCrCb for all standards
Single data rate (SDR) 24-bit 4:4:4 YCrCb/RGB for all
standards
Double data rate (DDR) 8-bit 4:2:2 YCrCb for all standards
Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all
standards
COMPOSITE AND S-VIDEO PROCESSING
Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N,
60) and SECAM B/D/G/K/L standards in the form of
CVBS and S-video
Superadaptive 2D 5-line comb filters for NTSC and PAL
give superior chrominance and luminance separation for
composite video
Full automatic detection and autoswitching of all
worldwide standards (PAL/NTSC/SECAM)
Automatic gain control with white peak mode ensures the
video is always processed without loss of the video
processing range
Adaptive digital line length tracking (ADLLT™)
Proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
IF filter block compensates for high frequency luma
attenuation due to tuner SAW filter
Chroma transient improvement (CTI)
Luminance digital noise reduction (DNR)
Color controls include hue, brightness, saturation, contrast,
and Cr and Cb offset controls
Certified Macrovision copy protection detection on
composite and S-video for all worldwide formats
(PAL/NTSC/SECAM)
4× oversampling (54 MHz) for CVBS, S-video, and YUV
modes
Line-locked clock output (LLC)
Letterbox detection supported
Free-run output mode provides stable timing when no
video input is present
Vertical blanking interval data processor
Tel eTe xt
Video Programming System (VPS)
Vertical Interval Time Codes (VITC)
Closed captioning (CC) and extended data service (EDS)
Wide screen signaling (WSS)
Copy generation management system (CGMS)
Gemstar™ 1×/2× electronic program guide compatible
Clocked from a single 28.63636 MHz crystal
Subcarrier frequency lock (SFL) output for downstream
video encoder
Differential gain typically 0.5%
Differential phase typically 0.5°
ADV7401
Rev. B | Page 14 of 20
COMPONENT VIDEO PROCESSING
Formats supported include 525i, 625i, 525p, 625p, 720p,
1080i, and many other HDTV formats
Automatic adjustments include gain (contrast) and offset
(brightness); manual adjustment controls are also
supported
Support for analog component YPrPb/RGB video formats
with embedded sync or with separate HS, VS, or CS
Any-to-any, 3 × 3 color space conversion matrix supports
YCrCb-to-RGB and RGB-to-YCrCb
Standard identification (STDI) enables system level
component format detection
Synchronization source polarity detector (SSPD) deter-
mines the source and polarity of the synchronization
signals that accompany the input video
Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
Free-run output mode provides stable timing when no
video input is present
Arbitrary pixel sampling support for nonstandard video
sources
RGB GRAPHICS PROCESSING
140 MSPS conversion rate supports RGB input resolutions
up to 1280 × 1024 @ 75 Hz (SXGA); (110 MSPS conversion
rate for ADV7401BSTZ-110); (80 MSPS conversion rate for
ADV7401BSTZ-80)
Automatic or manual clamp and gain controls for graphics
modes
Contrast and brightness controls
32-phase DLL allows optimum pixel clock sampling
Automatic detection of sync source and polarity by SSPD
block
Standard identification is enabled by STDI block
RGB can be color space converted to YCrCb and
decimated to a 4:2:2 format for video centric backend IC
interfacing
Data enable (DE) output signal supplied for direct
connection to HDMI/DVI Tx IC
Arbitrary pixel sampling support for nonstandard video
sources
DIGITAL VIDEO INPUT PORT
Supports raw 8-bit CVBS data from digital tuner
Support for 24-bit RGB input data from DVI Rx chip,
output converted to YCrCb 4:2:2
Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p,
1080i, 720p, VGA to SXGA @ 60 Hz input data from
HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb
GENERAL FEATURES
HS, VS, and FIELD output signals with programmable
position, polarity, and width
Programmable interrupt request output pin,
INT
, signals
SDP/CP status changes
Supports two I
2
C host port interfaces (control and VBI)
Low power consumption: 1.8 V digital core, 3.3 V analog
and digital I/O, low power power-down mode, and green
PC mode
Industrial temperature range (−40°C to +85°C)
(except ADV7401KSTZ-140)
140 MHz speed grade (ADV7401KST-140)
100-lead, 14 mm × 14 mm, Pb-free LQFP

ADV7401BSTZ-110

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10B Intg Multiformat SDTV/HDTV Decoder
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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