Serial Presence-Detect EEPROM
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 17: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
DDSPD
Parameter/Condition Symbol Min Max Units
Supply voltage V
DDSPD
3.0 3.6 V
Input low voltage: Logic 0; All inputs V
IL
–0.6 V
DDSPD
+ 0.3 V
Input high voltage: Logic 1; All inputs V
IH
V
DDSPD
+ 0.7 V
DDSPD
+ 1.0 V
Output low voltage: I
OUT
= 3mA V
OL
– 0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.1 2.0 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 2.0 µA
Table 18: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
Clock frequency
t
SCL 10 400 kHz
Clock pulse width HIGH time
t
HIGH 0.6 – µs
Clock pulse width LOW time
t
LOW 1.3 – µs
SDA rise time
t
R – 300 µs 1
SDA fall time
t
F 20 300 ns 1
Data-in setup time
t
SU:DAT 100 – ns
Data-in hold time
t
HD:DI 0 – µs
Data-out hold time
t
HD:DAT 200 900 ns
Data out access time from SCL LOW
t
AA:DAT 0.2 0.9 µs 2
Start condition setup time
t
SU:STA 0.6 – µs 3
Start condition hold time
t
HD:STA 0.6 – µs
Stop condition setup time
t
SU:STO 0.6 – µs
Time the bus must be free before a new transition can
start
t
BUF 1.3 – µs
WRITE time
t
W – 10 ms
Notes:
1. Guaranteed by design and characterization, not necessarily tested.
2. To avoid spurious start and stop conditions, a minimum delay is placed between the fall-
ing edge of SCL and the falling or rising edge of SDA.
3. For a restart condition, or following a WRITE cycle.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Serial Presence-Detect EEPROM
PDF: 09005aef837d3ecf
jtf8c128_256_512x64az.pdf - Rev. H 04/13 EN
16
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