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WM1824BGEDT/R

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
Production Data WM1824B
w
PD, Rev 4.0, November 2012
7
4. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with
mute applied.
WM1824B Production Data
w
PD, Rev 4.0, November 2012
8
POWER CONSUMPTION MEASUREMENTS
Test Conditions
LINEVDD=AVDD=DBVDD=3.3V, LINEGND=AGND=0V, T
A
=+25°C, quiescent (no signal)
TEST CONDITIONS
IAVDD
(mA)
ILINEVDD
(mA)
DBVDD
(mA)
TOTAL
(mA)
Off
No clocks applied 0.8
1.0 0.0 1.8
fs=48kHz, MCLK=256fs
Standby
MUTE ¯¯¯¯¯ = 0 0.2
2.1 0.02 2.32
Playback
MUTE ¯¯¯¯¯ = 1 4.7
6.0 0.02 10.72
fs=96kHz, MCLK=256fs
Standby
MUTE ¯¯¯¯¯ = 0 0.2
2.7 0.03 2.93
Playback
MUTE ¯¯¯¯¯ = 1 5.2
8.5 0.03 13.73
fs=192kHz, MCLK=128fs
Standby
MUTE ¯¯¯¯¯ = 0 0.2
2.7 0.04 2.94
Playback
MUTE ¯¯¯¯¯ = 1 5.2
8.4 0.04 13.64
Production Data WM1824B
w
PD, Rev 4.0, November 2012
9
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
LINEVDD=AVDD=DBVDD=2.97~3.63V, LINEGND=AGND=0V, T
A
=+25°C
PARAMETER SYMBOL MIN TYP MAX UNIT
Master Clock Timing Information
MCLK cycle time
t
MCLKY
27 500 ns
MCLK high time
t
MCLKH
11 ns
MCLK low time
t
MCLKL
11 ns
MCLK duty cycle (t
MCLKH
/t
MCLKL)
40:60 60:40 %
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

WM1824BGEDT/R

Mfr. #:
Buy WM1824BGEDT/R
Manufacturer:
Cirrus Logic
Description:
Audio D/A Converter ICs Stereo DAC w/ 2Vrms ground ref line Dvr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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