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IR3506MTRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
IR3506
Page 13 of 21 V3.02
PWM Ramp
Every time the phase IC is powered up, PWM ramp magnitude is calibrated to generate a 53 mV/%DC. For
example, for a 15 % duty ratio the ramp amplitude is 795mV.
In response to a load step-up, the error amplifier can demand 100 % duty cycle. In order to avoid pulse
skipping under this scenario and allow the BOOST cap to replenish, a minimum off-time is allowed in this
mode of operation. As shown in Figure 6, 100 % duty is detected by comparing the PWM latch output
(PWMQ) and its input clock (PWM_CLK). If the PWMQ is high when the PWM_CLK is asserted, the TopFET
turnoff is initiated. The TopFET is again turned on once the RMPOUT drops within 200 mV of the VDAC.
PHOUT
CLKIN
EAIN
(2 Phase Design)
RMPOUT
PWMQ
100 % DUTY OPERATIONNORMAL OPERATION
Figure 1: PWM Operation during normal and 100 % duty mode.
Power State Indicator (PSI) function
From a system perspective, the PSI input is controlled by the system and is forced low when the load current
is lower than a preset limit and forced high when load current is higher than the preset limit. IR3506 can
accept an active low signal on its PSI input and force the drivers into tri-state, effectively forcing the phase IC
into off state. A PSI-assert signal activates three features in the Phase IC.
1) It disconnects the IOUT pin from the IOUT bus: From a system perspective, IOUT is used to report current
and is used for over-current protection. By disconnecting the disabled phase from the IOUT bus, proper
current reporting and over-current protection level is ensured.
2) The DFF is disabled and it appears as a pass-through to the daisy chain loop: By removing the DFF from
the daisy chain, the system ensures that proper phase delay is activated among the active phases.
3) The gate drivers are forced to tri-state, effectively, disabling the phase IC: Figure 7 shows the impact of
PSI-assert on the gate drivers. After 8 cycle PHSIN delay, at the next CLK falling edge, the PSI_SYNC goes
from 0 to 1. This disables the gate drives and shorts the DFF.
IR3506
Page 14 of 21 V3.02
PSI_SYNC
PSI
8 PHSIN Delay
D_PWM LATCH
CLK
Figure 2: PSI assertion.
Debugging Mode
If CSIN+ pin is pulled up to VCCL voltage, IR3506 enters into debugging mode. Both drivers are pulled low
and IOUT output is disconnected from the current share bus, which isolates this phase IC from other phases.
However, the phase timing from PHSIN to PHSOUT does not change.
Emulated Bootstrap Diode
IR3506 integrates a PFET to emulate the bootstrap diode. If two or more top MOSFETs are to be driven at
higher switching frequency, an external bootstrap diode connected from VCCL pin to BOOST pin may be
needed.
Operation at Higher Output Voltage
The proper operation of the phase IC is ensured for maximum output voltage up to VCCL-2.5V if the differential
input (CSIN(+) – CSIN(-)) to current sense amplifier remain below 30 mV. Otherwise, the maximum voltage
output is calculated with the following equation:
),(*5.1max_
−+
−−−=
CSINCSIN
VVGcsVCCLVo
where, Gcs is the current sense amplifier gain (typically 32.5).
IR3506
Page 15 of 21 V3.02
DESIGN PROCEDURES - IR3506
Inductor Current Sensing Capacitor C
CS
and Resistor R
CS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor R
CS
and capacitor
C
CS
in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage
across the capacitor C
CS
represents the inductor current. If the two time constants are not the same, the AC
component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch
does not affect the average current sharing among the multiple phases, but does effect the current signal IOUT as
well as the output voltage during the load current transient if adaptive voltage positioning is adopted.
Measure the inductance L and the inductor DC resistance R
L
. Pre-select the capacitor C
CS
and calculate R
CS
as
follows.
CS
L
CS
C
RL
R =
(1)
Bootstrap Capacitor C
BST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
A 0.1uF-1uF decoupling capacitor is required at the VCCL pin.
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at
least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated.
The crossover frequency of current share loop
is approximately 8 kHz.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

IR3506MTRPBF

Mfr. #:
Buy IR3506MTRPBF
Manufacturer:
Infineon Technologies
Description:
Power Management Specialized - PMIC XPHASE3 DDR VTT 7V 2A 3 Wire
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New from this manufacturer.
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