Table 3: FBGA 63-Ball Descriptions
Symbol Type Description
A[14:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command.
BA[2:0] Input Bank address inputs: BA[2:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[2:0] define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE[1:0] Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE pow-
er-down (row active in any bank). CKE is synchronous for power-down entry, power-
down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF RE-
FRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_18 input but will detect a LVCMOS LOW level once V
DD
is applied during first pow-
er-up. After V
REF
has become stable during the power-on and initialization sequence, it
must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH
operation, V
REF
must be maintained.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-
nal bank selection on systems with multiple ranks. CS# is considered part of the com-
mand code.
DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls.
ODT[1:0] Input On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:
DQ[7:0], DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
DQ[3:0] I/O Data input/output: Bidirectional data bus for x4 configuration.
DQ[7:0] I/O Data input/output: Bidirectional data bus for x8 configuration.
DQS, DQS# I/O Data strobe: Output with read data, input with write data for source synchronous oper-
ation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
4Gb: x4, x8 TwinDie DDR2 SDRAM
Ball Assignments and Descriptions
PDF: 09005aef8227ee4d
mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
