MT47H512M8WTR-25E:C TR Datasheet MT47H1G4WTR-25E:C, MT47H1G4WTR-25E:C TR, MT47H512M8WTR-25E:C TR | P10-P12

Electrical Specifications – I

CDD

Parameters

Table 7: DDR2 I

DD

Specifications and Conditions (Die Revision C)

Notes: 1–8 apply to the entire table

Parameter/Condition

Com-

bined

Symbol

Individual

Die Status

Bus

Width

-25E/

-25 -3E/-3 Units

Operating one bank active-precharge current:

t

CK =

t

CK

(I

DD

),

t

RC =

t

RC (I

DD

),

t

RAS =

t

RAS MIN (I

DD

); CKE is HIGH, CS#

is HIGH between valid commands; address bus inputs are

switching; Data bus inputs are switching (inactive die is in

I

DD2P

condition, but with inputs switching)

I

CDD0

I

CDD0

=

I

DD0

+ I

CDD2P

x4, x8 92 87 mA

Operating one bank active-read-precharge current: I

OUT

= 0mA; BL = 4, CL = CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RC =

t

RC

(I

DD

),

t

RAS =

t

RAS MIN (I

DD

),

t

RCD =

t

RCD (I

DD

); CKE is HIGH,

CS# is HIGH between valid commands; address bus inputs are

switching; Data pattern is same as I

DD4W

(inactive die is in

I

DD2P

condition, but with inputs switching)

I

CDD1

I

CDD1

=

I

DD1

+ I

CDD2P

x4, x8 107 102 mA

Precharge power-down current: All banks idle;

t

CK =

t

CK

(I

DD

); CKE is LOW; Other control and address bus inputs are

stable; Data bus inputs are floating

I

CDD2P

I

CDD2P

=

I

DD2P

+ I

DD2P

x4, x8 24 24 mA

Precharge quiet standby current: All banks idle;

t

CK =

t

CK

(I

DD

); CKE is HIGH, CS# is HIGH; Other control and address bus

inputs are stable; Data bus inputs are floating

I

CDD2Q

I

CDD2Q

=

I

DD2Q

+ I

DD2P

x4, x8 47 42 mA

Precharge standby current: All banks idle;

t

CK =

t

CK (I

DD

);

CKE is HIGH, CS# is HIGH; Other control and address bus in-

puts are switching; Data bus inputs are switching (inactive

die is in I

DD2P

condition, but with inputs switching)

I

CDD2N

I

CDD2N

=

I

DD2N

+ I

CDD2P

x4, x8 52 47 mA

Active power-down current: All banks open;

t

CK =

t

CK (I

DD

); CKE is LOW; Other control and address bus in-

puts are stable; Data bus inputs are floating (individual die

status: I

CDD3P

= I

DD3P

+ I

DD2P

)

I

CDD3P

Fast PDN exit

MR[12] = 0

x4, x8 42 37 mA

Slow PDN exit

MR[12] = 1

x4, x8 26 26

Active power-down current: All banks open;

t

CK =

t

CK (I

DD

); CKE is LOW; Other control and address bus in-

puts are stable; Data bus inputs are floating (individual die

status: I

CDD3P

= I

DD3P

+ I

DD2P

)

I

CDD3N

I

CDD3N

=

I

DD3N

+ I

CDD2P

x4, x8 62 57 mA

Active standby current: All banks open;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX (I

DD

),

t

RP =

t

RP (I

DD

); CKE is HIGH, CS# is

HIGH between valid commands; Other control and address

bus inputs are switching; Data bus inputs are switching (inac-

tive die is in I

DD2P

condition, but with inputs switching)

I

CDD4W

I

CDD4W

=

I

DD4W

+ I

CDD2P

x4, x8 162 142 mA

Operating burst read current: All banks open, continuous

burst reads, Iout = 0mA; BL = 4, CL = CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX (I

DD

),

t

RP =

t

RP (I

DD

); CKE is HIGH,

CS# is HIGH between valid commands; address bus inputs are

switching; Data bus inputs are switching (inactive die is in

I

DD2P

condition, but with inputs switching)

I

CDD4R

I

CDD4R

=

I

DD4R

+ I

CDD2P

x4, x8 162 142 mA

4Gb: x4, x8 TwinDie DDR2 SDRAM

Electrical Specifications – I

CDD

Parameters

PDF: 09005aef8227ee4d

mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN

10

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 7: DDR2 I

DD

Specifications and Conditions (Die Revision C) (Continued)

Notes: 1–8 apply to the entire table

Parameter/Condition

Com-

bined

Symbol

Individual

Die Status

Bus

Width

-25E/

-25 -3E/-3 Units

Burst refresh current:

t

CK =

t

CK (I

DD

); refresh command at

every

t

RFC(I

DD

) interval; CKE is HIGH, CS# is HIGH between

valid commands; Other control and address bus inputs are

switching; Data bus inputs are switching (inactive die is in

I

DD2P

condition, but with inputs switching)

I

CDD5

I

CDD5

=

I

DD5

+ I

CDD2P

x4, x8 197 177 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other

control and address bus inputs are floating; Data bus inputs

are floating

I

CDD6

I

CDD6

=

I

DD6

+ I

DD6

x4, x8 24 24 mA

Operating bank interleave read current: All bank inter-

leaving reads, Iout = 0mA; BL = 4, CL = CL (I

DD

), AL =

t

RCD

(I

DD

) - 1 x

t

CK (I

DD

);

t

CK =

t

CK (I

DD

),

t

RC =

t

RC (I

DD

),

t

RRD =

t

RRD (I

DD

),

t

RCD =

t

RCD (Idd); CKE is HIGH, CS# is HIGH be-

tween valid commands; address bus inputs are stable during

deselects; Data bus inputs are switching (inactive die is in

I

DD2P

condition, but with inputs switching)

I

CDD7

I

CDD7

=

I

DD7

+ I

CDD2P

x4, x8 262 237 mA

Notes:

1. I

CDD

/I

DD

specifications are tested after the device is properly initialized. 0°C ≤ T

C

≤ +85°C.

V

DD

= V

DDQ

= +1.8V ±0.1V; V

DDL

= +1.8V ±0.1V; V

REF

= V

DDQ

/2.

2. I

CDD

/I

DD

parameters are specified with ODT disabled.

3. Data bus consists of DQ, DM, DQS, DQS#, RDQS, and RDQS#. Idd values must be met

with all combinations of EMR bits 10 and 11.

4. I

CDD

/I

DD

values must be met with all combinations of EMR bits 10 and 11.

5. Definitions for I

CDD

/I

DD

conditions:

LOW

V

IN(AC)

≤ V

IL(AC)max

HIGH V

IN

≥ V

IH(AC)min

Stable Inputs stable at a HIGH or LOW level

Floating Inputs at V

REF

= V

DDQ

/2

Switching Inputs changing between HIGH and LOW every other clock cycle (once per

two clocks) for address and control signals

Switching Inputs changing between HIGH and LOW every other data transfer (once

per clock) for DQ signals, not including masks or strobes

6. I

DD1

, I

DD4R

, and I

DD7

require A12 in EMR1 to be enabled during testing.

7. I

CDD

values reflect the combined current of both individual die. I

DDx

represents individual

die values.

8. The following I

DD

values must be derated (I

DD

limits increase) on IT-option or on AT-op-

tion devices when operated outside of the range 0°C ≤ T

C

≤ 85°C:

When

T

C

≤ 0°C

I

DD2P

and I

DD3P(SLOW)

must be derated by 4%; I

DD4R

and I

DD5W

must be derat-

ed by 2%; and I

DD6

and I

DD7

must be derated by 7%

When

T

C

≥ 85°C

I

DD0

, I

DD1

, I

DD2N

, I

DD2Q

, I

DD3N

, I

DD3P(FAST)

, I

DD4R

, I

DD4W

, and I

DD5W

must be de-

rated by 2%; I

DD2P

must be derated by 20%; I

DD3P

slow must be derated by

30%; and I

DD6

must be derated by 80% (I

DD6

will increase by this amount if

T

C

< 85°C and the 2X refresh option is still enabled)

4Gb: x4, x8 TwinDie DDR2 SDRAM

Electrical Specifications – I

CDD

Parameters

PDF: 09005aef8227ee4d

mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN

11

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Package Dimensions

Figure 5: 63-Ball FBGA (9mm x 11.5mm) (WTR)

Ball A1 ID

Seating

plane

0.12

A

0.8 ±0.1

1.2 MAX

0.25 MIN

9 ±0.15

Ball A1 ID

8 CTR

Solder ball

material: SAC305.

Dimensions apply

to solder balls

post-reflow on

Ø0.33 NSMD

ball pads.

63X Ø0.45

11.5 ±0.15

0.8 TYP

6.4 CTR

9 8 7 3 2 1

A

B

C

D

E

F

G

H

J

K

L

Note:

1. All dimensions are in millimeters.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

4Gb: x4, x8 TwinDie DDR2 SDRAM

Package Dimensions

PDF: 09005aef8227ee4d

mt47h1g_64m_32m_twindie.pdf - Rev. I 01/14 EN

12

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT47H512M8WTR-25E:C TR

MT47H512M8WTR-25E:C TR

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