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XR16M570IL24-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
XR16M570
19
REV. 1.0.1 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the
receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
address, it does not have to do anything. If the address does not match its slave address, then the receiver
should be disabled.
2.15.1 Auto Address Detection
Auto address detection mode is enabled when MSR[6] = 1 (requires EFR[4] = 1) and EFR bit-5 = 1. The
desired slave address will need to be written into the XOFF2 register. The receiver will try to detect an address
byte that matches the porgrammed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the receiver will discard
these data. Upon receiving an address byte that matches the XOFF2 character, the receiver will be
automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with
the parity bit (in place of the parity error bit). The receiver also generates an LSR interrupt. The receiver will
then receive the subsequent data. If another address byte is received and this address does not match the
programmed XOFF2 character, then the receiver will automatically be disabled and the address byte is
ignored. If the address byte matches XOFF2, the receiver will put this byte in the RX FIFO along with the parity
bit in the parity error bit.
2.16 Infrared Mode
The M570 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder sends out a
3/16 of a bit wide
HIGH-pulse for each “0” bit in the transmit data stream with a data rate up to 115.2 Kbps. For the IrDA 1.1
standard, the infrared encoder sends out a 1/4 of a bit time wide HIGH-pulse for each "0" bit in the transmit
data stream with a data rate up to 1.152 Mbps. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See
Figure 13 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. With this bit enabled, the
infrared encoder and decoder is compatible to the IrDA 1.0 standard. For the infrared encoder and decoder to
be compatible to the IrDA 1.1 standard, MSR bit-7 will also need to be set to a ’1’ when EFR bit-4 is set to ’1’.
Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 13.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
XR16M570
20
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.1
2.17 Sleep Mode with Auto Wake-Up and Power-Save feature
The M570 supports low voltage system designs, hence, a sleep mode with auto wake-up and power-save
feature is included to reduce its power consumption when the chip is not actively used.
2.17.1 Sleep mode
All of these conditions must be satisfied for the M570 to enter sleep mode:
■ no interrupts pending (ISR bit-0 = 1)
■ sleep mode is enabled (IER bit-4 = 1)
■ modem inputs are not toggling (MSR bits 0-3 = 0)
■ RX input pin is idling HIGH in normal mode or LOW in infrared mode
■ divisor is non-zero
■ TX and RX FIFOs are empty
The M570 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The M570 resumes normal operation by any of the following:
■ a receive data start bit transition (HIGH to LOW)
■ a data byte is loaded to the transmitter, THR or FIFO
■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the M570 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the M570 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
F
IGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
Start
Stop
0000 0
11 111
Bit Time
1/16 Clock Delay
IRdecoder-1
RX Data
Receive
IR Pulse
(RX pin)
Character
Data Bits
Start
Stop
0000 0
11 111
TX Data
Transmit
IR Pulse
(TX Pin)
Bit Time
1/2 Bit Time
3/16 or 1/4 Bit Time
IrEncoder-1
XR16M570
21
REV. 1.0.1 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
an interrupt is pending from any channel. The M570 will stay in the sleep mode of operation until it is disabled
by setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX pin is idling HIGH or “marking” condition
during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or another
type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the system design
engineer can use a 47k ohm pull-up resistor on each of the RX input.
2.17.2 Power-Save Feature
If the address lines, data bus lines, IOW#, IOR#, CS# and modem input lines remain steady when the M570 is
in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 41. If the input lines are floating or are toggling while the M570 is in sleep mode, the
current can be up to 100 times more. If not using the Power-Save feature, an external buffer would be required
to keep the address and data bus lines from toggling or floating to achieve the low current. But if the Power-
Save feature is enabled (PwrSave pin connected to VCC), this will eliminate the need for an external buffer by
internally isolating the address, data and control signals (see Figure 1 on page 1) from other bus activities that
could cause wasteful power drain. The M570 enters Power-Save mode when this pin is connected to VCC and
the M570 is in sleep mode (see Sleep Mode section above).
Since Power-Save mode isolates the address, data and control signals, the device will wake-up only by:
■ a receive data start bit transition (HIGH to LOW) at the RX input or
■ a change of logic state on the modem or general purpose serial input CTS#, DSR#, CD#, RI#
The M570 will return to the Power-Save mode automatically after a read to the MSR (to reset the modem input
CTS#) and all interrupting conditions have been serviced and cleared. The M570 will stay in the Power-Save
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the Power-Save pin is connected to
GND.
2.17.3 Wake-up Interrupt
The M570 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The
default status of wake up interrupt is disabled. Please See ”Section 4.5, FIFO Control Register (FCR) -
Write-Only” on page 29.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

XR16M570IL24-F

Mfr. #:
Buy XR16M570IL24-F
Manufacturer:
MaxLinear
Description:
UART Interface IC 1.8 HIGH PERFORMANCE UART W/16
Lifecycle:
New from this manufacturer.
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