XR16M570IL24-F Datasheet XR16M570IL24TR-F, XR16M570IL24-F, XR16M570IL32-F | P28-P30

XR16M570

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.1

4.4.2 Interrupt Clearing:

• LSR interrupt is cleared by a read to the LSR register.

• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

• RXRDY Time-out interrupt is cleared by reading RHR.

• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

• MSR interrupt is cleared by a read to the MSR register.

• Xon or Xoff interrupt is cleared by a read to the ISR register. See EMSR[7].

• Special character interrupt is cleared by a read to ISR register or after next character is received. See

EMSR[7].

• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

• Wakeup interrupt is cleared by a read to ISR register.

]

ISR[0]: Interrupt Status

• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

• Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 8).

ISR[4]: Interrupt Status (requires EFR bit-4 = 1)

This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match

of the Xoff, Xon or special character(s).

ISR[5]: Interrupt Status (requires EFR bit-4 = 1)

ISR bit-5 indicates that CTS# or RTS# has changed state from LOW to HIGH.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are

enabled.

ABLE 8: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY ISR REGISTER STATUS BITS SOURCE OF INTERRUPT

LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0

1 0 0 0 1 1 0 LSR (Receiver Line Status Register)

2 0 0 1 1 0 0 RXRDY (Receive Data Time-out)

3 0 0 0 1 0 0 RXRDY (Received Data Ready)

4 0 0 0 0 1 0 TXRDY (Transmit Ready)

5 0 0 0 0 0 0 MSR (Modem Status Register)

6 0 1 0 0 0 0 RXRDY (Received Xon, Xoff or Special character)

7 1 0 0 0 0 0 CTS#, RTS# change of state

- 0 0 0 0 0 1 None (default) or Wakeup interrupt

XR16M570

REV. 1.0.1 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

4.5 FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and

enable the wake up interrupt. They are defined as follows:

FCR[0]: TX and RX FIFO Enable

• Logic 0 = Disable the transmit and receive FIFO (default).

• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No receive FIFO reset (default)

• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No transmit FIFO reset (default).

• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: Enable wake up interrupt (requires EFR bit-4 = 1)

• Logic 0 = Disable the wake up interrupt (default).

• Logic 1 = Enable the wake up interrupt.

Please refer to “Section 2.17.3, Wake-up Interrupt” on page 21.

FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the

number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the

FIFO did not get filled over the trigger level on last re-load. Table 9

below shows the selections. Note that the

receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to

both the RX and TX side.

FCR[7:6]: Receive FIFO Trigger Select

These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when

the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.

Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last

applies to both the RX and TX side.

XR16M570

1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REV. 1.0.1

4.6 Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data

integrity check. See Table 10 for parity selection summary below.

• Logic 0 = No parity.

• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.

ABLE 9: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION

FCR BIT-7 FCR BIT-6 FCR BIT-5 FCR BIT-4

ECEIVE TRIGGER

LEVEL

TRANSMIT

TRIGGER LEVEL

COMPATIBILITY

1(default)

16L570

BIT-1 BIT-0 WORD LENGTH

0 0 5 (default)

01 6

10 7

11 8

BIT-2

ORD

LENGTH

STOP BIT LENGTH

(BIT TIME(S))

0 5,6,7,8 1 (default)

1 5 1-1/2

1 6,7,8 2

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P50

XR16M570IL24-F

Mfr. #:

Buy XR16M570IL24-F

Manufacturer:

MaxLinear

Description:

UART Interface IC 1.8 HIGH PERFORMANCE UART W/16

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

XR16M570IL24-F

XR16M570IL24-F

Products related to this Datasheet