XR16M570
23
REV. 1.0.1 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
3.0 UART INTERNAL REGISTERS
The complete register set for the M570 is shown in Table 6 and Table 7.
T
ABLE 6: UART INTERNAL REGISTERS
A2 A1 A0
ADDRESSES
R
EGISTER READ/WRITE COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0 DREV - Device Revision Read-only
LCR[7] = 1, LCR
≠ 0xBF,
DLL = 0x00, DLM = 0x00
0 0 1 DVID - Device Identification Register Read-only
0 0 0 DLL - Divisor LSB Register Read/Write
LCR[7] = 1, LCR
≠ 0xBF
See DLD[7:6]
0 0 1 DLM - Divisor MSB Register Read/Write
0 1 0 DLD - Divisor Fractional Register Read/Write LCR[7] = 1, LCR
≠ 0xBF,
EFR[4] = 1
0 0 0 RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0 0 1 IER - Interrupt Enable Register Read/Write
0 1 0 ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
LCR[7] = 0 if EFR[4] = 1
or
LCR
≠ 0xBF if EFR[4] = 0
0 1 1 LCR - Line Control Register Read/Write
1 0 0 MCR - Modem Control Register Read/Write
LCR
≠ 0xBF1 0 1 LSR - Line Status Register Read-only
1 1 0 MSR - Modem Status Register Read-only
1 1 0 MSR - Modem Status Register Write-only LCR
≠ 0xBF
EFR[4] = 1
1 1 1 SPR - Scratch Pad Register Read/Write LCR
≠ 0xBF, FCTR[6] = 0
1 1 1 EMSR - Enhanced Mode Select Register Write-only
LCR
≠ 0xBF, FCTR[6] = 1
1 1 1 FC - RX/TX FIFO Level Counter Register Read-only
ENHANCED REGISTERS
0 0 0 FC - RX/TX FIFO Level Counter Register Read-only
LCR = 0xBF
0 0 1 FCTR - Feature Control Register Read/Write
0 1 0 EFR - Enhanced Function Reg Read/Write
1 0 0 Xon-1 - Xon Character 1 Read/Write
1 0 1 Xon-2 - Xon Character 2 Read/Write
1 1 0 Xoff-1 - Xoff Character 1 Read/Write
1 1 1 Xoff-2 - Xoff Character 2 Read/Write
