Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. C
12/11/06
IS41LV16100B ISSI
®
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval:
—
Auto refresh Mode: 1,024 cycles /16 ms
—
RAS-Only, CAS-before-RAS (CBR), and Hidden
— Self refresh Mode: 1,024 cycles /128 ms
• JEDEC standard pinout
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Industrial Temperature Range: -40
o
C to +85
o
C
• Lead-free available
DESCRIPTION
The ISSI IS41LV16100B is 1,048,576 x 16-bit high-perfor-
mance CMOS Dynamic Random Access Memories. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 1,024 random ac-
cesses within a single row with access cycle time as short
as 20 ns per 16-bit word.
These features make the IS41LV16100B ideally suited for
high-bandwidth graphics, digital signal processing, high-
performance computing systems, and peripheral
applications.
The IS41LV16100B is packaged in a 42-pin 400-mil SOJ
and 400-mil 50- (44-) pin TSOP (Type II).
1M x 16 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
Max. RAS Access Time (tRAC) 5060ns
Max. CAS Access Time (tCAC) 1415ns
Max. Column Address Access Time (tAA)2530ns
Min. EDO Page Mode Cycle Time (tPC)3040ns
Min. Read/Write Cycle Time (tRC) 85 110 ns
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II) 42-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9 Address Inputs
I/O0-15 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
VDD Power
GND Ground
NC No Connection
DECEMBER 2006
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
