XRD9824
16
Rev. 2.00
Internal CIS Reference Circuit (DB 4 = 1)
The XRD9824 has an internal register reserved for
interfacing to the Canon CIS model number CVA-
60216K. When this register is selected, the VDCEXT
(Pin 16) becomes an output voltage of 1.24 volts. This
voltage can be directly connected to the VREF (Pin 15)
of the Canon sensor. This reduces the amount of
Figure 10. Typical Application Circuitry Internal CIS Reference Circuit Mode
CANON CIS Sensor, Model #CVA=60216k
components needed for biasing the Canon CIS sensor
(the external diodes and resistors typically used in this
application have been included inside the XRD9824 for
this mode of operation). Below is a typical application
circuit using the XRD9824 and the Canon CVA-
60216K CIS sensor.
AGND
DVDD (3V - 5V)
VCC (5V)
AVDD
DGND
AGND
DGND
DGND
DGND
DGND
DVDD (3V - 5V)
ASIC
DIGITAL
N/C
N/C
CANON CIS
SENSOR
0.1uF
0.01uF
0.1uF
0.01uF
0.1uF
XRD9824
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAMP
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
CVA-60216K
VOUT
1
MODE
2
AGND
3
VCC
4
VREF
5
SP
6
CLK
7
LED COM
8
LED BLU
9
LED GRN
10
LED RED
11
FGND
12
10K
10K
10K
47uF
47uF
NPN
NPN
NPN
0.01uF
100uF
XRD9824
17
Rev. 2.00
Figure 11. Typical Application Circuitry Internal CIS Rotating
Gain and Offset Line-By-Line
CIS Line-By-Line Rotating Gain and Offset
(Configuration DB1 = 1, DB0 = 1)
Line-by-line rotating gain and offset minimizes the
amount of write cycles per scan. Pre-loaded values of
gain and offset can be loaded for each color before the
first line is scanned. Each gain and offset is cycled
AVDD
AGND
DGND
VCC (5V - 15V)
DVDD (3V - 5V)
ASIC
DIGITAL
C
I
S
N/C
0.01uF
0.1uF
0.1uF
0.1uF
XRD9824
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAMP
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
0.01uF
through line-by-line so that the gain and offset do not
have to be loaded in between lines. Below is the typical
application circuit and timing for this configuration.
XRD9824
18
Rev. 2.00
Figure 12. Timing Diagram for Figure 11
CCD Configuration (Charge Coupled Device)
Mode 1. AC Coupled
In the CCD configuration of operation, an external
capacitor needs to be chosen according to the equa-
tions below. The typical value for the external capaci-
tor is 100pF. This value should be adjusted according
to the time constant (Tc) needed in a particular appli-
cation. The CLAMP pin has an internal 150 ohm
impedance (R
INT
) which is in series with the external
capacitor (C
EXT
).
Therefore, Tc =1/R
INT
C
EXT
If the input to the external capacitor has a load imped-
ance (R
EXT
), then
T
c
=1/(R
INT
+R
EXT
)C
EXT
When CLAMP (clamp) pin is set high an internal switch
allows one side of the external capacitor to be set to
VRT (Figure 13). This value corresponds to the black
reference of the CCD. When the CLAMP pin is set
back to low, the ADC samples the video signal with
respect to the black reference. The difference between
the black reference and the video signal is the actual
pixel value of the video content. Since this value is
referenced to the top ladder reference voltage of the
ADC a zero input signal would yield a full scale output
code. Therefore, the output of the conversion is
inverted (internally) to correspond to zero scale output
code.
CIS Rotating Gain and Offset
Line-By-Line (Md 11)
ADCCLK
CIS
SYNCH
GAIN/
OFFSET
LD
Red Pixel Line Scan Grn Pixel Line Scan Blu Pixel Line Scan
Red Gain/Offset Cycle Grn Gain/Offset Cycle Blu Gain/Offset Cycle
Reset Internal Mux Color to Red Channel (LD = 110YYYYYY11)
tsa
tsypw
Note:
Y = Previous State
Tri-State (SYNCH = LO)

XRD9824ACD-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
Analog to Digital Converters - ADC
Lifecycle:
New from this manufacturer.
Delivery:
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