XRD9824
26
Rev. 2.00
Mode 2. DC Coupled
Typical CCDs have outputs with black references.
Therefore, DC Coupled is not recommended for CCD
applications.
Offset Control DAC
The offset DAC is controlled by 8 bits. The offset range
is 800 mV ranging from -200 mV to +600 mV (when
DB5 is set to 0) and -400 mV to +400 mV (when DB5
is set to 1). Therefore, the resolution of the 8-Bit offset
DAC is 3.14 mV. However, the XRD9824 has +/- 100
mV reserved for internal offsets. Therefore, the effec-
tive range for adjusting for CIS offsets or black refer-
ence is 600 mV. The offset adjustment is used prima-
rily to correct for the difference between the black level
of the image sensor and the bottom ladder reference
voltage (VRB) of the ADC. By adjusting the black level
to correspond to VRB, the entire range of the ADC can
be used.
If the offset of the CIS output is greater than 500 mV an
external reference can be applied to VDCEXT. The
external reference can be used to adjust for large
offsets only when the internal mode is configured
through the serial port.
Since the offset DAC adjustment is done before the
gain stage, it is gain-dependent. For example, if the
gain needs to be changed between lines (red to blue,
etc.), the offset is calibrated before the signal passes
through the PGA.
PGA (Programmable Gain Amplifier) DAC
The gain of the input waveform is controlled by a 6-Bit
PGA. The PGA is used along with the offset DAC for
the purpose of using the entire range of the ADC. The
PGA has a linear gain from 1 to 10. Figure 19 is a plot
of the transfer curve for the PGA gain.
PGA GAIN TRANSFER CURVE
GAIN 1 - 10
1
2
3
4
5
6
7
8
9
10
0 102030405060
CODE
GAIN
Figure 20. Transfer Curve for the 6-Bit PGA
After the signal is level shifted to correspond with the
bottom ladder reference voltage, the system can be
calibrated such that a white video pixel can represent
the top ladder reference voltage to the ADC. This
allows for a full scale conversion maximizing the reso-
lution of the ADC.
Analog to Digital Converter
The ADC is a 14-bit, 10 MSPS analog-to-digital con-
verter for high speed and high accuracy. The ADC
uses a subranging architecture to maintain low power
consumption at high conversion rates. The output of
the ADC is on 8-bit databus. The 8-bit databus sup-
ports 8x6 output data. ADCCLK samples the input on
its falling edge. After the input is sampled, the MSB is
latched to the output drivers. On the rising edge of the
ADCCLK, the LSB is latched to the output drivers. The
output needs to be demultiplexed with external circuitry
or a digital ASIC. There is an 8 clock cycle latency
(Config 00, 11) or 6 pixel count latency (Config 01, 10)
for the analog-to-digital converter.
The V
RT
and V
RB
reference voltages for the ADC are
generated internally, unless the external V
RT
is se-
lected. In the external V
RT
mode, the V
RT
voltage is set
through the VREF+ pin. This allows the user to select
the dynamic range of the ADC.
