XRD9824
29
Rev. 2.00
Function
(Register
S2/S1/S0) D7 D6 D5 D4 D3 D2 D1 D0 Power-up
State
(Note 1)
Red Gain G5 G4 G3 G2 G1 G0 X X 000000XX
(000) (MSB) (LSB)
Red Offset O7 O6 O5 O4 O3 O2 O1 O0 01000000
(001) (MSB) (LSB)
Grn Gain G5 G4 G3 G2 G1 G0 X X 000000XX
(010) (MSB) (LSB)
Grn Offset
(011) O7 O6 O5 O4 O3 O2 O1 O0 01000000
(MSB) (LSB)
Blu Gain
(100) G5 G4 G3 G2 G1 G0 X X 000000XX
(MSB) (LSB)
Blu Offset
(101) O7 O6 O5 O4 O3 O2 O1 O0 01000000
(MSB) (LSB)
Mode POWER DIGITAL V
RT
INPUT DC DC/AC SIGNAL SIGNAL 00000000
(110) DOWN RESET REFERENCE POLARITY CONFIGURATION
(V
DCREF
)
0: NORMAL 0: NO RESET 0: INTERNAL 0: INTERNAL 0: DC 0: Non- 00: Single-Channel
(V
DCREF
=AGND) Inverted RED input/gain/offset
1: 1:RESET 1: EXTERNAL 1: EXTERNAL 1: AC (CIS)
POWER (REGISTERS (V
DCREF
=V
DCEXT
) 1: Inverted 01: Single-Channel
DOWN ARE RESET TO (CCD/CIS) RED input
POWER-UP RED/GRN/BLU
STATES) gain/offset cycle
pixel-by-pixel
10: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
pixel-by-pixel
11: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
line-by-line
Mode TEST5 OUTPUT OFFSET INTERNAL CIS TEST4 TEST3 TEST2 TEST1 00000000
&Test DISABLE DAC REFERENCE
(111) RANGE CIRCUIT
0:NORMAL 0:OUTPUTS 0:-200mV to 0:NORMAL 0: TEST4 0: TEST3 0: TEST2 0:NORMAL
ENABLED +600mV DISABLED DISABLED DISABLED
1:NOT USED 1:OUTPUTS 1:-400mV to 1:REFERENCE 1: OUTPUT 1: OUTPUT 1: INPUT 1: TEST1
DISABLED +400mV CIRCUIT OF BUFFER OF PGA OF ADC ENABLED
ENABLED TIED TO TIED TO TIED TO
BLU VDCEXT GRN
Control Registers
