NCV8509 Series
http://onsemi.com
12
CIRCUIT DESCRIPTION
Figure 41. Dual Drive RESET Valid
V
IN
V
OUT1
RESET
Power Up Short on
V
OUT1
V
IN1
Fast
Turn Off
RESET
Output Peak
Reset Delay Reset Delay Reset Delay
RESET
The RESET function gets its drive from both the input
(V
IN1
) and the output (V
OUT1
). Because of this, it is able to
maintain a more reliable reset valid signal. Most regulators
maintain a valid reset signal down to 1 V on the output
voltage. The reset on the NCV8509 is valid down to 0 V on
the output voltage V
OUT1
(power is provided via V
IN1
) and
the reset on the NCV8509 is valid down to 0 V on the input
voltage V
IN1
(power is provided via V
OUT1
). Refer to
Figure 41 for operation timing diagrams.
Delay Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET
output lead.
The delay lead provides source current (typically 6.0 μA)
to the external delay capacitor during the following
proceedings:
1. During power up (once the regulation threshold
has been verified);
2. After a reset event has occurred and the device is
back in regulation.
The delay capacitor is discharged when the regulation
(RESET
threshold) has been violated. This is a latched
incident. The capacitor will fully discharge and wait for the
device to regulate before going through the delay time event
again.
Power Shunt
R
EX
routes some of the current used in the V
OUT2
to a
second input pin (V
IN2
). This is accomplished by using an
internal shunt. A simplified version of this shunt is shown in
Figure 42. This has the effect of reducing the amount of
power dissipated on chip. The effects of choosing the
external resistor value are shown in Figure 43.
Selection of the optimum Rex resistor value can be done
using the following equation:
(V
in(max)
* 4.5)
I
out2(max)
When not using the power shunt, short V
IN1
to V
IN2
.
