NCV8509PDW18R2 Datasheet NCV8509PDW25R2G, NCV8509PDW26R2G, NCV8509PDW18G | P13-P15

NCV8509 Series

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13

Figure 42. Power Shunt

R

EX

V

IN1

V

IN2

V

OUT2

Voltage

Regulator

Figure 43. Power On Chip

0

V

IN

0.2

0.4

0.6

0.8

1.0

1.2

1.8

Watts

5 10152025

1.4

1.6

R

EX

> 138

R

EX

= 138

R

EX

< 138

I

OUT2

= 100 mA

Figure 44.

135 Ω

V

IN1

18 V

V

IN2

4.5 V

R

LOAD

V

OUT2

2.5 V

100 mA

135 Ω

V

IN1

6.0 V

V

IN2

3.1 V

R

LOAD

V

OUT2

2.5 V

21.5 mA

135 Ω

V

IN1

6.0 V

V

IN2

4.5 V

R

LOAD

V

OUT2

2.5 V

100 mA

78.5 mA

+

600 mV

−

Figure 45. Figure 46.

21.5 mA100 mA 21.5 mA

Why Use a Power Shunt?

The power shunt circuitry helps manage and optimize

power dissipation on the integrated circuit.

Figure 44 shows a 100 mA load. A 135 Ω resistor

dissipates 1.35 W as shown.

Without the power shunt, the 135 Ω resistor would run

into head room issues at 6.0 V and would only be able to

drive 21.5 mA as shown in Figure 45 before causing the

2.5 V output to collapse.

Figure 46 shows the power shunt circuitry adding the

current back in at low voltage operation. So the power is

moved off chip at high voltage where it is needed most.

To further clarify, Figure 47 shows the maximum allowed

resistor value (29 Ω) without the power shunt for 6.0 V

operation.

Figure 48 shows the scenario at high voltage. Only 290 mW

of power is dissipated off chip compared to Figure 44 with

1.35 W.

Figure 47.

29 Ω

V

IN1

18 V

V

IN2

15.1 V

R

LOAD

V

OUT2

2.5 V

100 mA

Figure 48.

29 Ω

V

IN1

6.0 V

V

IN2

3.1 V

R

LOAD

V

OUT2

2.5 V

100 mA

+

600 mV

−

100 mA 100 mA

NCV8509 Series

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14

Power Dissipation

NCV8509 has a power shunt circuit which reduces the

power on chip by utilizing an external resistor, R

EX

. Thus

the power on chip, P

IC

, is equal to the total power, P

T

, minus

the power dissipated in the resistor P

REX

. Refer to Figure 49.

P

IC

+ P

TOTAL

* P

REX

(1)

where

(2)

P

TOTAL

+ (V

IN1

* V

OUT1)

I

OUT1

) (V

IN1

* V

OUT2

)I

OUT2

) (V

IN1

Iq)

and

P

REX

+ (V

IN1

* V

IN2

)I

OUT2

(3)

Figure 49.

NCV8509

Control

Circuitry

I

OUT2

I

OUT1

Iq

V

OUT1

GND

V

OUT2

Q3Q2

Q1

R

EX

V

Z

V

IN2

V

IN1

Shunt

V

SAT

+

−

ȧ

ȥ

ȡ

Ȣ

IN1 SAT

V

REF

V

IN1

* (I

OUT2

R

EX

)

(4)

V

IN2

+

for V

IN1

t (V

REF

) V

SAT

)

for (V

REF

) V

SAT

) t V

IN1

t (V

REF

) (I

OUT2

R

EX

))

for (V

REF

) (I

OUT2

I

OUT

)) t V

IN1

where V

REF

= V

Z

− V

BE

when Q1 is normally conducting.

Based on equation 3, the power in R

EX

is dependent on

V

IN2

. (Increasing R

EX

may require an increase in C

IN2

. A

careful system validation should be performed for stability).

The voltage on V

IN2

is controlled by the shunt circuit, which

has three modes of operation, as seen in Figure 50.

Mode 1. At low battery V

IN2

is equal to V

IN1

minus the

saturation voltage of the shunt output NPN.

Mode 2. Once V

IN1

rises above the reference voltage of

the shunt circuit, V

IN2

will regulate at the V

REF

.

Mode 3. V

IN2

would continue to regulate at V

REF

, but

since I

OUT2

is not infinite, when V

IN1

rises higher than the

reference voltage plus the voltage drop across the external

resistor R

EX

, it will force V

IN2

to be V

IN1

− (I

OUT2

× R

EX

).

Equation 4 provides a summary for V

IN2.

Combining equations 3 and 4 gives three different

equations for power across R

EX

.

P

MODE1

+ (V

SAT

I

OUT2

)

(5)

P

MODE2

+ (V

IN1

* V

REF

) I

OUT2

(6)

P

MODE3

+ I

OUT2

2

R

EX

(7)

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15

Figure 50. V

IN

Shunt

Max V

IN

Delta

I(V

IN2

) × R

EX

Shunt Off

Shunt On

V

IN2

V

IN1

4.5 V

Mode 1

Mode 2

Mode 3

V

IN1

t V

REF

) V

SAT

V

IN2

+ V

IN1

* V

SAT

V

REF

) V

SAT

t V

IN1

t V

REF

) (I

OUT2

R

EX

)

V

IN2

+ V

REF

V

IN1

u V

REF

) (I

OUT2

R

EX

)

V

IN2

+ V

IN1

* (I

OUT2

R

EX

)

Figure 51. 16 Lead SOW (Exposed Pad), qJA as a

Function of the Pad Copper Area (2 oz. Cu

Thickness), Board Material = 0.0625, G−10/R−4

40

70

90

100

Thermal Resistance,

Junction to Ambient, R

q

JA

, (°C/W)

0

Copper Area (mm

2

)

200 400 800

80

60

50

600

Once the value of P

IC(max)

is known, the maximum

permissible value of R

q

JA

can be calculated:

R

qJA

+

150

C *

T

A

P

IC

(8)

The value of R

q

JA

can then be compared with those in the

package section of the data sheet. Those packages with

R

q

JA

’s less than the calculated value in equation 2 will keep

the die temperature below 150°C.

In some cases, none of the packages will be sufficient to

dissipate the heat generated by the IC, and an external

heatsink will be required.

Heat Sinks

A heat sink effectively increases the surface area of the

package to improve the flow of heat away from the IC and

into the surrounding air.

Each material in the heat flow path between the IC and the

outside environment will have a thermal resistance. Like

series electrical resistances, these resistances are summed to

determine the value of R

q

JA

:

R

qJA

+ R

qJC

) R

qCS

) R

qSA

(9)

where:

R

q

JC

= the junction−to−case thermal resistance,

R

q

CS

= the case−to−heatsink thermal resistance, and

R

q

SA

= the heatsink−to−ambient thermal resistance.

R

q

JC

appears in the package section of the data sheet. Like

R

q

JA

, it too is a function of package type. R

q

CS

and R

q

SA

are

functions of the package type, heatsink and the interface

between them. These values appear in heat sink data sheets

of heat sink manufacturers.

NCV8509PDW18R2

NCV8509PDW18R2

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