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ADG3249BRJ-R2

P1-P3P4-P6P7-P9P10-P12P13-P13
REV. 0
ADG3249
2.5 V/3.3 V, 2:1 Multiplexer/
Demultiplexer Bus Switch
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
225 ps Propagation Delay through the Switch
4.5 Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
8-Lead SOT-23 Package
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Docking Stations
Memory Switching
Analog Switch Applications
FUNCTIONAL BLOCK DIAGRAM
EN
ADG3249
A0
A1
B
CONTROL
LOGIC
IN
GENERAL DESCRIPTION
The ADG3249 is a 2.5 V or 3.3 V, high performance 2:1 multi-
plexer/demultiplexer bus switch. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. This allows the
input to be connected to the output without additional propaga-
tion delay or generating additional ground bounce noise.
Each switch of the ADG3249 conducts equally well in both direc-
tions when on. The ADG3249 exhibits break-before-make
switching action, preventing momentary shorting when switch-
ing channels.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from
3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device
is operated from 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition, a level
translating pin (SEL) is included. When SEL is low, V
CC
is
reduced internally, allowing for level translating between 3.3 V
inputs and 1.8 V outputs.
The ADG3249 is available in a tiny 8-lead SOT-23 package.
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Tiny SOT-23 package.
ADG3249* Product Page Quick Links
Last Content Update: 11/01/2016
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Documentation
Data Sheet
• ADG3249: 2.5 V/3.3 V, 2:1 Multiplexer/Demultiplexer Bus
Switch Data Sheet
Reference Materials
Product Selection Guide
• Switches and Multiplexers Product Selection Guide
Technical Articles
• CMOS Switches Offer High Performance in Low Power,
Wideband Applications
• Data-acquisition system uses fault protection
Design Resources
• ADG3249 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all ADG3249 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
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number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
REV. 0–2–
ADG3249–SPECIFICATIONS
1
B Version
Parameter Symbol Conditions Min Typ
2
Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
INH
V
CC
= 2.7 V to 3.6 V 2.0 V
V
INH
V
CC
= 2.3 V to 2.7 V 1.7 V
Input Low Voltage V
INL
V
CC
= 2.7 V to 3.6 V 0.8 V
V
INL
V
CC
= 2.3 V to 2.7 V 0.7 V
Input Leakage Current I
I
± 0.01 ± 1 µA
OFF State Leakage Current I
OZ
0 ≤ A, B ≤ V
CC
± 0.01 ± 1 µA
ON State Leakage Current 0 ≤ A, B ≤ V
CC
± 0.01 ±1 µA
Maximum Pass Voltage V
P
V
A
/V
B
= V
CC
= SEL = 3.3 V, I
O
= –5 µA 2.0 2.5 2.9 V
V
A
/V
B
= V
CC
= SEL = 2.5 V, I
O
= –5 µA1.51.82.1V
V
A
/V
B
= V
CC
= 3.3 V, SEL = 0 V, I
O
= –5 µA 1.5 1.8 2.1 V
CAPACITANCE
3
A Port Off Capacitance C
A
OFF f = 1 MHz; EN = V
CC
3.5 pF
B Port Off Capacitance C
B
OFF f = 1 MHz; EN = V
CC
4.5 pF
A, B Port On Capacitance C
A
, C
B
ON f = 1 MHz 8.5 pF
Control Input Capacitance C
IN,
C
SEL
f = 1 MHz 4 pF
C
EN
f = 1 MHz 6.5 pF
SWITCHING CHARACTERISTICS
3
Propagation Delay A to B or B to A, t
PD
4
t
PHL
, t
PLH
C
L
= 50 pF, V
CC
= SEL = 3 V 0.225 ns
Propagation Delay Matching
5
5ps
Bus Enable Time EN to A or B
6
t
PZH
, t
PZL
V
CC
= 3.0 V to 3.6 V; SEL = V
CC
1 3.5 4.8 ns
Bus Disable Time EN to A or B
6
t
PHZ
, t
PLZ
V
CC
= 3.0 V to 3.6 V; SEL = V
CC
1 5.5 8.2 ns
Bus Enable Time EN to A or B
6
t
PZH
, t
PZL
V
CC
= 3.0 V to 3.6 V; SEL = 0 V 1 3.2 4.5 ns
Bus Disable Time EN to A or B
6
t
PHZ
, t
PLZ
V
CC
= 3.0 V to 3.6 V; SEL = 0 V 1 4.5 7.7 ns
Bus Enable Time EN to A or B
6
t
PZH
, t
PZL
V
CC
= 2.3 V to 2.7 V; SEL = V
CC
1 3.5 4.6 ns
Bus Disable Time EN to A or B
6
t
PHZ
, t
PLZ
V
CC
= 2.3 V to 2.7 V; SEL = V
CC
14 5.8 ns
Break-before-Make Time t
BBM
R
L
= 510 Ω, C
L
= 50 pF 5 10 ns
Transition Time t
TRANS
R
L
= 510 Ω, C
L
= 50 pF; SEL = V
CC
16 29 ns
R
L
= 510 Ω, C
L
= 50 pF; SEL = 0 V 15 22 ns
Maximum Data Rate V
CC
= SEL = 3.3 V; V
A
/V
B
= 2 V 1.244 Gbps
Channel Jitter V
CC
= SEL = 3.3 V; V
A
/V
B
= 2 V 45 ps p-p
DIGITAL SWITCH
On Resistance R
ON
V
CC
= 3 V, SEL = V
CC
, V
A
= 0 V, I
BA
= 8 mA 4.5 8 Ω
V
CC
= 3 V, SEL = V
CC
, V
A
= 1.7 V, I
BA
= 8 mA 12 28 Ω
V
CC
= 2.3 V, SEL = V
CC
, V
A
= 0 V, I
BA
= 8 mA 5 9 Ω
V
CC
= 2.3 V, SEL = V
CC
, V
A
= 1 V, I
BA
= 8 mA 9 18 Ω
V
CC
= 3 V, SEL = 0 V V
A
= 0 V, I
BA
= 8 mA 5 8 Ω
V
CC
= 3 V, SEL = 0 V, V
A
= 1 V, I
BA
= 8 mA 12 Ω
On Resistance Matching ⌬R
ON
V
CC
= 3 V, SEL = V
CC
, V
A
= 0 V, I
A
= 8 mA 0.1 0.5 Ω
V
CC
= 3 V, SEL = 0 V, V
A
= 0 V, I
A
= 8 mA 0.1 0.5 Ω
POWER REQUIREMENTS
V
CC
2.3 3.6 V
Quiescent Power Supply Current I
CC
Digital Inputs = 0 V or V
CC
; SEL = V
CC
0.01 1 µA
Digital Inputs = 0 V or V
CC
; SEL = 0 V 0.1 0.2 mA
Increase in I
CC
per Input
7
⌬I
CC
V
CC
= 3.6 V, EN = 3.0 V; SEL = V
CC
; IN = V
CC
0.15 8 µA
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Typical values are at 25°C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical R
ON
of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information section.
7
This current applies to the control pin EN only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
(V
CC
= 2.3 V to 3.6 V, GND = 0 V, all specifications T
MIN
to T
MAX
,
unless otherwise noted.)
P1-P3P4-P6P7-P9P10-P12P13-P13

ADG3249BRJ-R2

Mfr. #:
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Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 2.5V/3.3V 2:1 w/ Bus Switch
Lifecycle:
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