REV. 0
ADG3249
–9–
BUS SWITCH APPLICATIONS
Mixed Voltage Operation, Level Translation
Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3249 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 2.5 V to 1.8 V, or bidirectionally from 3.3 V directly
to 2.5 V.
Figure 4 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V toler-
ant inputs, therefore placing the ADG3249 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
3.3V ADC
2.5V
3.3V
2.5V
MICROPROCESSOR
ADG3249
3.3V
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
3.3 V to 2.5 V Translation
When V
CC
is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to V
CC
, the maximum output signal will be clamped to
within a voltage threshold below the V
CC
supply. In this case,
the output will be limited to 2.5 V, as shown in Figure 6. This
device can be used for translation from 2.5 V to 3.3 V devices
and also between two 3.3 V devices.
ADG3249
2.5V
2.5V
3.3V
2.5V
3.3V
Figure 5. 3.3 V to 2.5 V Voltage Translation,
SEL
= V
CC
V
IN
2.5V
V
OUT
0V
3.3V
SWITCH
INPUT
SWITCH
OUTPUT
3.3V SUPPLY
SEL = 3.3V
Figure 6. 3.3 V to 2.5 V Voltage Translation,
SEL
= V
CC
2.5 V to 1.8 V Translation
When V
CC
is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to V
CC
, the maximum output signal will, as before, be clamped
to within a voltage threshold below the V
CC
supply. In this case,
the output will be limited to approximately 1.8 V, as shown
in Figure 8.
ADG3249
1.8V
2.5V
2.5V
Figure 7. 2.5 V to 1.8 V Voltage Translation,
SEL
= 2.5 V
CC
V
IN
1.8V
V
OUT
0V
2.5V
SWITCH
INPUT
SWITCH
OUTPUT
2.5V SUPPLY
SEL = 2.5V
Figure 8. 2.5 V to 1.8 V Voltage Translation,
SEL
= V
CC
3.3 V to 1.8 V Translation
The ADG3249 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin. The SEL pin is an active low control pin. SEL acti-
vates internal circuitry in the ADG3242 that allows voltage
translation between 3.3 V devices and 1.8 V devices.
When V
CC
is 3.3 V and the input signal range is 0 V to V
CC
, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
SEL is unused, it should be tied directly to V
CC
.
ADG3249
1.8V
3.3V
3.3V
Figure 9. 3.3 V to 1.8 V Voltage Translation,
SEL
= 0 V
V
IN
1.8V
V
OUT
0V
3.3V
SWITCH
INPUT
SWITCH
OUTPUT
3.3V SUPPLY
SEL = 0V
Figure 10. 3.3 V to 1.8 V Voltage Translation,
SEL
= 0 V
REV. 0–10–
ADG3249
Analog Switching
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
Multiplexing
Many systems, such as docking stations and memory banks,
have a large number of common bus signals. Common prob-
lems faced by designers of these systems include
Large delays caused by capacitive loading of the bus
Noise due to simultaneous switching of the address and data
bus signals
Figure 11 shows an array of memory banks in which each ad-
dress and data signal is loaded by the sum of the individual
loads. If a bus switch is used as shown in Figure 12, the output
load on the memory address and data bits is halved. The speed
at which the selected banks data can flow is much improved
because the capacitance loading is halved and the switches
introduce negligible propagation delay. Bus noise is also reduced.
High Impedance during Power-Up/Power-Down
To ensure the high impedance state during power-up or power-
down, EN should be tied to V
CC
through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
MEMORY
ADDRESS
DATA
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
MEMORY
BANK A
Figure 11. All Memory Banks Are Permanently
Connected to the Bus
MEMORY
ADDRESS
DATA
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
MEMORY
BANK A
ADG3249
ADG3249
Figure 12. ADG3249 Used to Reduce Both Access
Time and Noise
REV. 0
ADG3249
–11–
OUTLINE DIMENSIONS
8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
1 3
5 6
2
8
4
7
2.90 BSC
PIN 1
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8
4
0
2.80 BSC
COMPLIANT TO JEDEC STANDARDS MO-178BA

ADG3249BRJ-R2

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 2.5V/3.3V 2:1 w/ Bus Switch
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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