LTC2444/LTC2445/
LTC2448/LTC2449
13
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Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 38) is used to
synchronize the data transfer. Each bit of data is shifted
out the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2444/LTC2445/LTC2448/LTC2449
create their own serial clock. In the External SCK mode
of operation, the SCK pin is used as input. The internal or
external SCK mode is selected by tying EXT (Pin 3) LOW
for external SCK and HIGH for internal SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 37), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO
pin is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 36) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH
on the SDO pin. Once the conversion is complete, EOC
goes LOW. The device remains in the sleep state until the
first rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 36), is used to test the
conversion status and to enable the data output transfer
as described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer
has been completed. The LTC2444/LTC2445/LTC2448/
LTC2449 will abort any serial data transfer in progress
and start a new conversion cycle anytime a LOW-to-HIGH
transition is detected at the CS pin after the converter has
entered the data output state.
Serial Data Input (SDI)
The serial data input (SDI, Pin 34) is used to select the
speed/resolution and input channel of the LTC2444/
LTC2445/LTC2448/LTC2449. SDI is programmed by a
serial input data stream under the control of SCK during
the data output cycle, see Figure 3.
Initially, after powering up, the device performs a conver
-
sion with IN
+
= CH0, IN
= CH1, OSR = 256 (output rate
nominally 880Hz), and 1X speed mode (no latency). Once
this first conversion is complete, the device enters the
sleep state and is ready to output the conversion result
and receive the serial data input stream programming the
speed/resolution and input channel for the next conversion.
At the conclusion of each conversion cycle, the device
enters this state.
In order to change the speed/resolution or input chan
-
nel, the first 3 bits shifted into the device are 101. This
is compatible with the programming sequence of the
LTC2414/LTC2418. If the sequence is set to 000 or 100,
the following input data is ignored (dont care) and the
previously selected speed/resolution and channel remain
valid for the next conversion. Combinations other than
101, 100, and 000 of the 3 control bits should be avoided.
If the first 3 bits shifted into the device are 101, then the
following 5 bits select the input channel for the following
conversion (see Tables 3 and 4). The next 5 bits select the
speed/resolution and mode 1X (no latency) 2X (double
output rate with one conversion latency), see Table 5. If
these 5 bits are set to all 0s, the previous speed remains
selected for the next conversion. This is useful in appli
-
cations requiring a fixed output rate/resolution but need
to change the
input channel. In this case,
the timing and
input sequence is compatible with the LTC2414/LTC2418.
When an update operation is initiated (the first 3 bits are
101) the first 5 bits are the channel address. The first
bit, SGL, determines if the input selection is differential
(SGL =
0) or single-ended (SGL = 1). For SGL
= 0, two
adjacent channels can be selected to form a differential
input. For SGL = 1, one of 8 channels (LTC2444/LTC2445)
or one of 16 channels (LTC2448/LTC2449) is selected as
the positive input. The negative input is COM for all single
ended operations. The remaining 4 bits (ODD, A2, A1,
A0) determine which channel is selected. The LTC2448/
LTC2449 use all 4 bits to select one of 16 different input
channels (see Table 3) while in the case of the LTC2444/
LTC2445, A2 is always 0, and the remaining 3 bits select
one of 8 different input channels (see Table 4).
LTC2444/LTC2445/
LTC2448/LTC2449
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Table 3. Channel Selection for the LTC2448/LTC2449
MUX ADDRESS CHANNEL SELECTION
SGL
ODD/
SIGN A2 A1 A0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COM
0 0 0 0 0 IN
+
IN
0 0 0 0 1 IN
+
IN
0 0 0 1 0 IN
+
IN
0 0 0 1 1 IN
+
IN
0 0 1 0 0 IN
+
IN
0 0 1 0 1 IN
+
IN
0 0 1 1 0 IN
+
IN
0 0 1 1 1 IN
+
IN
0 1 0 0 0 IN
IN
+
0 1 0 0 1 IN
IN
+
0 1 0 1 0 IN
IN
+
0 1 0 1 1 IN
IN
+
0 1 1 0 0 IN
IN
+
0 1 1 0 1 IN
IN
+
0 1 1 1 0 IN
IN
+
0 1 1 1 1 IN
IN
+
1 0 0 0 0 IN
+
IN
1 0 0 0 1 IN
+
IN
1 0 0 1 0 IN
+
IN
1 0 0 1 1 IN
+
IN
1 0 1 0 0 IN
+
IN
1 0 1 0 1 IN
+
IN
1 0 1 1 0 IN
+
IN
1 0 1 1 1 IN
+
IN
1 1 0 0 0 IN
+
IN
1 1 0 0 1 IN
+
IN
1 1 0 1 0 IN
+
IN
1 1 0 1 1 IN
+
IN
1 1 1 0 0 IN
+
IN
1 1 1 0 1 IN
+
IN
1 1 1 1 0 IN
+
IN
1 1 1 1 1 IN
+
IN
*Default at power up
LTC2444/LTC2445/
LTC2448/LTC2449
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Table 4. Channel Selection for the LTC2444/LTC2445 (Bit A2 Should Always Be 0)
MUX ADDRESS CHANNEL SELECTION
SGL ODD/SIGN A2 A1 A0 0 1 2 3 4 5 6 7 COM
0 0 0 0 0 IN
+
IN
0 0 0 0 1 IN
+
IN
0 0 0 1 0 IN
+
IN
0 0 0 1 1 IN
+
IN
0 1 0 0 0 IN
IN
+
0 1 0 0 1 IN
IN
+
0 1 0 1 0 IN
IN
+
0 1 0 1 1 IN
IN
+
1 0 0 0 0 IN
+
IN
1 0 0 0 1 IN
+
IN
1 0 0 1 0 IN
+
IN
1 0 0 1 1 IN
+
IN
1 1 0 0 0 IN
+
IN
1 1 0 0 1 IN
+
IN
1 1 0 1 0 IN
+
IN
1 1 0 1 1 IN
+
IN
*Default at power up
Table 5. LTC2444/LTC2445/LTC2448/LTC2449 Speed/Resolution Selection
OSR3 OSR2 OSR1 OSR0 TWOX
RMS NOISE
LTC2444/LTC2448
RMS NOISE
LTC2445/LTC2449
ENOB
LTC2444/LTC2448
ENOB
LTC2445/LTC2449 OSR LATENCY
0 0 0 0 0 Keep Previous Speed/Resolution
0 0 0 1 0 23µV 23µV 17 17 64 none
0 0 1 0 0 4.4µV 3.5µV 20.1 20.1 128 none
0 0 1 1 0 2.8µV 2µV 20.8 21.3 256 none
0 1 0 0 0 2µV 1.4µV 21.3 21.8 512 none
0 1 0 1 0 1.4µV 1µV 21.8 22.4 1024 none
0 1 1 0 0 1.1µV 750nV 22.1 22.9 2048 none
0 1 1 1 0 720nV 510nV 22.7 23.4 4096 none
1 0 0 0 0 530nV 375nV 23.2 24 8192 none
1 0 0 1 0 350nV 250nV 23.8 24.4 16384 none
1 1 1 1 0 280nV 200nV 24.1 24.6 32768 none
0 0 0 0 1 Keep Previous Speed/Resolution
0 0 0 1 1 23µV 23µV 17 17 64 1 cycle
0 0 1 0 1 4.4µV 3.5µV 20.1 20.1 128 1 cycle
0 0 1 1 1 2.8µV 2µV 20.8 21.3 256 1 cycle
0 1 0 0 1 2µV 1.4µV 21.3 21.8 512 1 cycle
0 1 0 1 1 1.4µV 1µV 21.8 22.4 1024 1 cycle
0 1 1 0 1 1.1µV 750nV 22.1 22.9 2048 1 cycle
0 1 1 1 1 720nV 510nV 22.7 23.4 4096 1 cycle
1 0 0 0 1 530nV 375nV 23.2 24 8192 1 cycle
1 0 0 1 1 350nV 250nV 23.8 24.4 16384 1 cycle
1 1 1 1 1 280nV 200nV 24.1 24.6 32768 1 cycle

LTC2448IUHF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-Bit 8-ch. Diff., High Speed Delta-Sigma ADC
Lifecycle:
New from this manufacturer.
Delivery:
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