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LTC2448IUHF#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
LTC2444/LTC2445/
LTC2448/LTC2449
19
2444589fc
For more information www.linear.com/LTC2444
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
7. CS may be permanently tied to ground, simplifying the
user interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. Conversely, BUSY (Pin 2) may be used
to monitor the status of the conversion cycle. EOC or
BUSY may be used as an interrupt to an external control
-
applicaTions inForMaTion
ler
indicating the conversion result is ready.
EOC
= 1
(BUSY = 1) while the conversion is in progress and
EOC
=0 (BUSY = 0) once the conversion enters the low
power sleep state. On the falling edge of
EOC
/BUSY, the
conversion result is loaded into an internal static shift
register. The device remains in the sleep state until the
first rising edge of SCK. Data is shifted out the SDO pin
on each falling edge of SCK enabling external circuitry to
latch data on the rising edge of SCK.
EOC
can be latched
on the first rising edge of SCK. On the 32nd falling edge
of SCK, SDO and BUSY go HIGH (
EOC
=1) indicating a
new conversion has begun.
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
2444589 F07
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB
SIG
BIT 29
“0”
BIT 30
EOC
BIT 31
1 0 EN SGL A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 32
DON'T CAREDON'T CARE
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
BUSY
LTC2444/LTC2445/
LTC2448/LTC2449
20
2444589fc
For more information www.linear.com/LTC2444
applicaTions inForMaTion
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode,
the EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alterna
-
tively, BUSY (Pin 2) may be used to monitor the status
of the conversion in progress. BUSY is HIGH during the
conversion and goes LOW
at the conclusion. It remains
LOW until the result is read from the device.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit the sleep state and enter the data
output state if CS remains LOW. In order to prevent the
device from exiting the low power sleep state, CS must
be pulled HIGH before the first rising edge of SCK. In the
internal SCK timing mode, SCK goes HIGH and the device
begins outputting data at time t
EOCtest
after the falling edge
of CS (if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is
LOW during the falling edge of EOC). The value of t
EOCt-
est
is 500ns. If CS is pulled HIGH before time t
EOCtest
, the
device remains in the sleep state. The conversion result
is held in the internal static shift register.
Figure 8. Internal Serial Clock, Single Cycle Operation
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB
Hi-Z
2444589 F08
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
CS
SCK
SDI
SDO
BUSY
BIT 31
1 0 EN SGL A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 32
CONVERSION
SLEEP DATA OUTPUT
CONVERSION
TEST EOC TEST EOC
DON'T CARE DON'T CARE
<t
EOC(TEST)
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
BUSY
LTC2444/LTC2445/
LTC2448/LTC2449
21
2444589fc
For more information www.linear.com/LTC2444
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
on this first rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. Thirteen
serial input data bits are required in order to properly pro-
gram the speed/resolution and input channel. If the data
output sequence is aborted
prior to the 13th rising edge
of SCK, the new input data is ignored, and the previously
selected speed/resolution and channel are used for the next
conversion cycle.
If a new channel is being programmed,
the rising edge of
CS
must come after the 14th falling
edge of SCK in order to store the data input sequence.
applicaTions inForMaTion
Figure 9. Internal Serial Clock, Reduced Data Output Length
CS
SCK
SDI
SDO
BUSY
1 2 3 4 5 6 1 5
MSB
BIT 28 BIT 27 BIT 26 BIT 25
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z Hi-Z
BIT 31
2444589 F09
CONVERSION
SLEEP
SLEEP
DATA OUTPUT DATA OUTPUT
CONVERSION
CONVERSION
TEST EOC
DON'T CARE DON'T CARE DON'T CARE
<t
EOC(TEST)
<t
EOC(TEST)
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
BUSY
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

LTC2448IUHF#TRPBF

Mfr. #:
Buy LTC2448IUHF#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-Bit 8-ch. Diff., High Speed Delta-Sigma ADC
Lifecycle:
New from this manufacturer.
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