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LTC2448IUHF#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
LTC2444/LTC2445/
LTC2448/LTC2449
22
2444589fc
For more information www.linear.com/LTC2444
applicaTions inForMaTion
Internal Serial Clock, 2-Wire I/O, Continuous
Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, sim
-
plifying the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW (EOC
= 0) indicating the conversion has finished and the device
has entered the low power sleep state. The part remains in
the sleep state a minimum amount of time (≈500ns) then
immediately begins outputting data. The data output cycle
begins on the first rising edge of SCK and ends after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
Figure 10. Internal Serial Clock, Continuous Operation
CS
SCK
SDI
SDO
BUSY
2444589 F10
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0
LSB
SIG
BIT 29
“0”
BIT 30
EOC
BIT 31
1 0 EN SGL A2 A1 A0 OSR3 OSR2 OSR1 OSR0 TWOXODD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 32
DON'T CAREDON'T CARE
V
CC
F
O
REF
+
REF
–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28 35
29
30
8
15
16
23
7
38
37
1,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUTS
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1µF
4.5V TO 5.5V
LTC2448
4-WIRE
SPI INTERFACE
•
•
•
•
•
•
•
•
•
•
•
•
BUSY
LTC2444/LTC2445/
LTC2448/LTC2449
23
2444589fc
For more information www.linear.com/LTC2444
applicaTions inForMaTion
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2444/LTC2445/
LTC2448/LTC2449 significantly simplify antialiasing filter
requirements.
The LTC2444/LTC2445/LTC2448/LTC2449’s speed/
resolution is determined by the over sample ratio (OSR)
of the on-chip digital filter. The OSR ranges from 64 for
3.5kHz output rate to 32,768 for 6.9Hz (in No Latency
mode) output rate. The value of OSR and the sample rate
f
S
determine the filter characteristics of the device. The first
NULL of the digital filter is at f
N
and multiples of f
N
where
f
N
= f
S
/OSR, see Figure 11 and Table 7. The rejection at
the frequency f
N
±14% is better than 80dB, see Figure12.
If F
O
is grounded, f
S
is set by the on-chip oscillator at
1.8MHz (over supply and temperature variations). At an
OSR of 32,768, the first NULL is at f
N
= 55Hz and the
no latency output rate is f
N
/8 = 6.9Hz. At the maximum
OSR, the noise performance of the device is 280nV
RMS
(LTC2444/LTC2448) and 200nV
RMS
(LTC2445/LTC2449)
Table 7. OSR vs Notch Frequency (f
N
) (with Internal Oscillator
Running at 9MHz)
OSR NOTCH (f
N
)
64 28.16kHz
128 14.08kHz
256 7.04kHz
512 3.52kHz
1024 1.76kHz
2048 880Hz
4096 440Hz
8192 220Hz
16384 110Hz
32768* 55Hz
*Simultaneous 50/60Hz rejection
Figure 11. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (Internal Oscillator)
Figure 12. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (Internal Oscillator)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
180
2444589 F11
–80
–100
60 120
240
–120
–140
–20
NORMAL MODE REJECTION (dB)
SINC
4
ENVELOPE
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
47
–140
NORMAL MODE REJECTION (dB)
–130
–120
–110
–100
51 55
59
63
2440 F12
–90
–80
49 53
57
61
LTC2444/LTC2445/
LTC2448/LTC2449
24
2444589fc
For more information www.linear.com/LTC2444
applicaTions inForMaTion
clock applied to F
O
results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 14. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
An external oscillator operating from 100kHz to 12MHz can
be implemented using the LTC1799 (resistor set SOT-23
oscillator), see Figure 17. By floating pin 4 (DIV) of the
LTC1799, the output oscillator frequency is:
f
MHz
k
R
OSC
SET
=
10
10
10
•
•
The normal mode rejection characteristic shown in
Figure13 is achieved by applying the output of the LTC1799
(with R
SET
= 100k) to the F
O
pin on the LTC2444/LTC2445/
LTC2448/LTC2449 with SDI tied HIGH (OSR = 32768).
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
2444589 F13
–80
–100
1000000
2000000
–120
1.8MHz
–140
–20
NORMAL MODE REJECTION (dB)
REJECTION > 120dB
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–40
–20
0
8
2444589 F14
–60
–80
2 4 6
10
–100
–120
–140
NORMAL MODE REJECTION (dB)
Figure 13. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (Internal Oscillator)
Figure 14. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (External Oscillator at 90kHz)
with better than 80dB rejection of 50Hz ±2% and 60Hz ±2%.
Since the OSR is large (32,768) the wide band rejection
is extremely large and the antialiasing requirements are
simple. The first multiple of f
S
occurs at 55Hz • 32,768 =
1.8MHz, see Figure 13.
The first NULL becomes f
N
= 7.04kHz with an OSR of 256
(an output rate of 880Hz) and F
O
grounded. While the NULL
has shifted, the sample rate remains constant. As a result
of constant modulator sampling rate, the linearity, offset
and full-scale performance remains unchanged as does
the first multiple of f
S
.
The sample rate f
S
and NULL f
N
, may also be adjusted by
driving the F
O
pin with an external oscillator. The sample
rate is f
S
= f
EOSC
/5, where f
EOSC
is the frequency of the
clock applied to F
O
. Combining a large OSR with a reduced
sample rate leads to notch frequencies f
N
near DC while
maintaining simple antialiasing requirements. A 100kHz
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

LTC2448IUHF#TRPBF

Mfr. #:
Buy LTC2448IUHF#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-Bit 8-ch. Diff., High Speed Delta-Sigma ADC
Lifecycle:
New from this manufacturer.
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