NCN5121
www.onsemi.com
19
The third limit on VFILT capacitor value is the required
capacitor value to filter out current steps DI
step
of the system
without going into reset.
C u
DI
step
2
ǒ
2 @ (V
BUS1
* V
coupler_drop
* V
FILTL
) @ I
slope
Ǔ
The last condition on the size of VFILT is the desired
warning time t
warning
between SAVEB and RESETB in case
the bus voltage drops away. This is determined by the current
consumption of the system I
system
.
C u I
system
ǒ
t
warning
) t
busfilter
Ǔ
ǒ
V
BUS1
* V
coupler_drop
* V
FILTL
Ǔ
The bus coupler is implemented as a linear voltage
regulator. For efficiency purpose, the voltage drop over the
bus coupler is kept minimal (see Table 4).
KNX Impedance Control
The impedance control circuit defines the impedance of
the bus device during the active and equalization pulses. The
impedance can be divided into a static and a dynamic
component, the latter being a function of time. The static
impedance defines the load for the active pulse current and
the equalization pulse current. The dynamic impedance is
produced by a block, called an equalization pulse generator,
that reduces the device current consumption (i.e. increases
the device impedance) as a function of time during the
equalization phase so as to return energy to the bus.
Fixed and Adjustable DC−DC Converter
The device contains two DC−DC buck converters, both
supplied from VFILT.
DC1 provides a fixed voltage of 3.3 V. This voltage is used
as an internal low voltage supply (V
DDA
and V
DDD
) but can
also be used to power external devices (VDD1−pin). DC1 is
automatically enabled during the power−up procedure (see
Analog State Diagram, p23).
DC2 provides a programmable voltage by means of an
external resistor divider. It is not used as an internal voltage
supply making it not mandatory to use this DC−DC
converter (if not needed, tie the VDD2MV pin to VDD1, see
also Figure 12).
DC2 can be monitored (<VDD2>, see System Status
Service, p37), and/or disabled by a command from the host
controller (<DC2EN>, see Analog Control Register 0, p54).
DC2 will only be enabled when VFILT−bit is set (<VFILT>,
see System Status Service, p37). The status of DC2 can be
monitored (<VDD2>, see System Status Service, p37).
The voltage divider can be calculated as follows:
(eq. 1)
R
4
+ R
5
V
VDD2
* 1.2
1.2
Both DC−DC converters make use of slope control to
improve EMC performance (see Table 5). To operate DC1
and DC2 correctly, the voltage on the VIN−pin should be
higher than the highest value of DC1 and DC2.
Although both DC−DC converters are capable of
delivering 100 mA, the maximum current capability will not
always be usable. One always needs to make sure that the
KNX bus power consumption stays within the KNX
specification. The maximum allowed current for the DC−DC
converters and V20V regulator can be estimated as next:
V
BUS
ǒ
I
BUS
* I
20V
Ǔ
2
ƪ
ǒ
V
DD1
I
DD1
Ǔ
)
ǒ
V
DD2
I
DD2
Ǔ
ƫ
w 1
(eq. 2)
I
BUS
will be limited by the KNX standard and should be
lower or equal to I
coupler
(see Table 4). Minimum V
BUS
is
20 V (see KNX standard). V
DD1
and V
DD2
can be found back
in Table 4. I
DD1
, I
DD2
and I
20V
must be chosen in a correct
way to be in line with the KNX specification (Note 2).
Although DC2 can operate up to 21 V, it will not be
possible to generate this 21 V under all operating conditions.
See application note AND9135 for defining the optimum
inductor and capacitor of the DC−DC converters. When
using low series resistance output capacitors on DC2, it is
advised to split the current sense resistor as shown in
Figure 18 to reduce ripple current for low load conditions.
V20V Regulator
This is the 20 V low drop linear voltage regulator used to
supply external devices. As it draws current from VFILT,
this current is seen without any power conversion directly at
the VBUS1 pin.
The V20V regulator starts up by default but can be
disabled by a command from the host controller
(<V20VEN>, see Analog Control Register 0, p54). When
the V20V regulator is not used, no load capacitor needs to
be connected (see C7 of Figures 12, 13 and 14). Connect
V20V−pin with VFILT−pin in this case.
V20V regulator will only be enabled when VFILT−bit is
set (<VFILT>, see System Status Service, p37). The host
controller can also monitor the status of the regulator
(<V20V>, see System Status Service, p37). The 20 V
regulator has a current limit that depends on the FANIN resistor
value, and the value of bits 0−3 (V20VCLIMIT[0:2]) of the
analog control register. In Table 4, the typical value of the
current limit at startup is given as I
20V_lim
(V20VCLIMIT[0:2]
initializes at 100). For each bit difference, the current limit
is adjusted up or down by DI
20
V, S T E P
.
Xtal Oscillator
An analog oscillator cell generates the main clock of
16 MHz. This clock is directly provided to the digital block
to generate all necessary clock domains.
An input pin XSEL is foreseen to enable the use of a quartz
crystal (see Figure 16) or an external clock generator (see
Figure 17) to generate the main clock.
2. The formula is for a typical KNX application. It‘s only given as guidance and does not guarantee compliance with the KNX standard.
