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NCN5121MNTWG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P58
NCN5121
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28
SPI Interface
The SPI interface is selected by MODE1− and
MODE2−pin. The baudrate is determined by which
MODE−pin is pulled high (MODE1 pulled high = 125 kbps,
MODE2 pulled high = 500 kbps).
The SPI interface allows full duplex synchronous
communication between the device and the host controller.
The interface operates in Mode 0 (CPOL and CPHA = ‘0’)
meaning that the data is clocked out on the falling edge and
sampled on the rising edge. The LSB is transmitted first.
SCK
SDI
CSB
LSB 1 2 3 4 5 6 MSBSDO
10 32 54 76
LSB 1 2 3 4 5 6 MSB
Figure 25. SPI Transfer
During SPI transmission, data is transmitted (shifted out
serially) on the SDO/TXD−pin and received (shifted in
serially) on the SDI/RXD−pin simultaneously. SCK/UC2 is
set as output and is used as the serial clock (SCK) to
synchronize shifting and sampling of the data on the SDI−
and SDO−pin. The speed of this clock signal is selectable
(see Table 9). The slave select line (CSB/UC1−pin) will go
low during each transmission allowing to selection the host
controller (CSB−pin is high when SPI is in idle state).
Shift Register
Control
NCN5121
SDO/TXD
SDI/RXD
SCK/UC2
CSB/UC1
Shift Register
Host Controller
MISO
MOSI
SCLK
SS
Control
Figure 26. SPI Master
In an SPI network only one SPI Master is allowed (in this
case NCN5121). To allow the host controller to
communicate with the device the TREQ−pin can be used
(Transmit Request). When NCN5121 detects a negative
edge on TREQ, the device will issue dummy transmission
of 8 bits which will result in a transmission of data byte from
the host controller to the device. See Figure 11 for details on
the timings. See Figure 13 for an SPI application example.
SCK
SDI
CSB
SDO
TREQ
01234567
DDDDDDDD
01234
DDDDD
Dummy
Start dummy transmission
Figure 27. Transmission Request
NCN5121
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29
DIGITAL FUNCTIONAL DESCRIPTION
The implementation of the Data Link Layer as specified in the KNX standard is divided in two parts. All functions related
to communication with the Physical Layer and most of the Data Link Layer services are inside NCN5121, the rest of the
functions and the upper communication layers are implemented into the host controller (see Figure 28).
The host controller is responsible for handling:
• Checksum
• Parity
• Addressing
• Length
The NCN5121 is responsible for handling:
• Checksum
• Parity
• Acknowledge
• Repetition
• Timing
Digital State Diagram
The digital state diagram is given in Figure 29.
The current mode of operation can be retrieved by the host controller at any time (when RESETB−pin is high) by issuing
the U_SystemStat.req service and parsing back U_SystemStat.ind service (see System Status Service, p37).
Table 10. NCN5121 DIGITAL STATES
State Explanation
RESET Entered after Power On Reset (POR) or in response to a U_Reset.req service issued by the host controller. In this
state NCN5121 gets initialized, all features disabled and services are ignored and not executed.
POWER−UP /
POWER−UP
STOP
Entered after Reset State or when VBUS, VFILT or Xtal are not operating correctly (operation of VBUS, VFILT and
XTAL can be verified by means of the System Status Service, p37). Communication with KNX bus is not allowed.
U_SystemStat.ind can be used to verify this state (code 00).
SYNC NCN5121 remains in this state until it detects silence on the KNX bus for at least 40 Tbits. Although the receiver of
NCN5121 is on, no frames are transmitted to the host controller.
U_SystemStat.ind can be used to verify this state (code 01).
STOP This state is useful for setting−up NCN5121 safely or temporarily interrupting reception from the KNX bus.
U_SystemStat.ind can be used to verify this state (code 10).
NORMAL In this state the device is fully functional. Communication with the KNX bus is allowed.
U_SystemStat.ind can be used to verify this state (code 11).
NCN5121
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30
Application Layer
Presentation Layer
Session Layer
Transport Layer
Network Layer
Data Link Layer
Logic Link Control
Media Access Control
Physical Layer
7
6
5
4
3
2
1
NCN5121 Host Controller
Figure 28. OSI Model Reference
Reset
Initialize device
Deactivate all features
POR or U_Reset.req
Power−Up
Code: 00
KNX Rx = off
KNX Tx = off
Sync
Code: 01
KNX Rx = on
KNX Tx = off
Stop
Code: 10
KNX Rx = off
KNX Tx = off
Normal
Code: 11
KNX Rx = on
KNX Tx = on
Power−Up Stop
Code: 00
KNX Rx = off
KNX Tx = off
<XTAL>=‘1’
and
<VBUS> = ‘1’
and
<VFILT> = ‘1’
<XTAL>=‘0’
or
<VBUS> = ‘0’
or
<VFILT> = ‘0’
<XTAL> =‘1’
and
<VBUS> = ‘1’
and
<VFILT> = ‘1’
<XTAL> = ‘0’
or
<VBUS> = ‘0’
or
<VFILT> = ‘0’
<XTAL> = ‘0’
or
<VBUS> = ‘0’
or
<VFILT> = ‘0’
Send U _Reset .ind
to host
KNX bus idle for w40 Tbits
U_ExitStopMode.req
Send U_StopMode.ind
to host
U_StopMode.req
U_StopMode.req and
no activity for w30 Tbits
U_ExitStopMode .req
Send U_StopMode.ind
to host
U_StopMode .req
Figure 29. Digital State Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P58

NCN5121MNTWG

Mfr. #:
Buy NCN5121MNTWG
Manufacturer:
ON Semiconductor
Description:
Communication ICs - Various KNXB
Lifecycle:
New from this manufacturer.
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