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52
Host Ctrl NCN5121 KNX Bus
1 1 1 1 0 0 0 0
Control Byte
x x x x x x x x
Source Address
x x x x x x x x
Checksum
1 1 1 1 0 0 0 0
L_Poll_Data.ind
1 1 1 0 s s s s
U_PollingState.req
x x x x x x x x
Slot 0
x x x x x x x x
Poll Address
x x x x x x x x
Source Address
x x x x x x x x
PollAddrLow
x x x x x x x x
Poll Address
x x x x x x x x
Poll Address
x x x x x x x x
Slot Count
x x x x x x x x
PollState
x x x x x x x x
Slot N
x x x x x x x x
Source Address
x x x x x x x x
PollAddrHigh
x x x x x x x x
Source Address
x x x x x x x x
Poll Address
x x x x x x x x
Slot Count
x x x x x x x x
Checksum
x x x x x x x x
Slot 0
x x x x x x x x
Slot N
1 1 1 1 0 0 0 0
Control Byte
x x x x x x x x
Source Address
x x x x x x x x
Checksum
x x x x x x x x
Source Address
x x x x x x x x
Poll Address
x x x x x x x x
Poll Address
x x x x x x x x
Slot Count
Figure 57. Master Polling Frame Service
Remarks:
x = don‘t care (in respect with KNX standard)
ssss = slot number
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53
CRC−CCITT
CRC order - 16 bit
CRC polynom (hex) - 1021
Initial value (hex) − FFFF
Final XOR value (hex) − 0
No reverse on output CRC
Test string „123456789“ is 29B1h
CRC−CCITT value over a buffer of bytes can be calculated with following code fragment in C, where
pBuf is pointer to the start of frame buffer
uLength is the frame length in bytes
unsigned short calc_CRC_CCITT(unsigned char* pBuf, unsigned short uLength)
{
unsigned short u_crc_ccitt;
for (u_crc_ccitt = 0xFFFF; uLength−−; p++)
{
u_crc_ccitt = get_CRC_CCITT(u_crc_ccitt, *p);
}
return u_crc_ccitt;
}
unsigned short get_CRC_CCITT(unsigned short u_crc_val, unsigned char btVal)
{
u_crc_val = ((unsigned char)(u_crc_val >> 8)) | (u_crc_val << 8);
u_crc_val ^= btVal;
u_crc_val ^= ((unsigned char)(u_crc_val & 0xFF)) >> 4;
u_crc_val ^= u_crc_val << 12;
u_crc_val ^= (u_crc_val & 0xFF) << 5;
return u_crc_val;
}
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Internal Device−Specific Registers
In total 4 device-specific register are available:
Watchdog Register (0x00)
Analog Control Register 0 (0x01)
Analog Control Register 1 (0x02)
Analog Status Register 0 (0x03)
Revision ID Register (0x05)
Watchdog Register
The Watchdog Register is located at address 0x00 and can be used to enable the watchdog and set the watchdog time.
Table 14. WATCHDOG REGISTER
ExtWatchdogCtrl (ExtWR)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x00
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 1 1 1 1
Data WDEN - - - WDT
Table 15. WATCHDOG REGISTER PARAMETERS
Parameter Value Description Info
WDEN
0 Disable
Enables/disables the watchdog
p22
1 Enable
WDT
0000 33 ms
Defines the watchdog time. The watchdog needs to be re-enabled (WDEN)
within this time or a watchdog event will be triggered.
0001 66 ms
0010 98 ms
0011 131 ms
0100 164 ms
0101 197 ms
0110 229 ms
0111 262 ms
1000 295 ms
1001 328 ms
1010 360 ms
1011 393 ms
1100 426 ms
1101 459 ms
1110 492 ms
1111 524 ms
Remark: Bit 4 6 are reserved.
Analog Control Register 0
The Analog Control Register 0 is located at address 0x01 and can be used to disable the V20V and the DC2 regulator, to
disable the XCLK-pin, to enable the transmit trigger signal and to set the 20 V LDO current limit.
Table 16. ANALOG CONTROL REGISTER 0
Analog Control Register 0 (AnaCtrl0)
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x01
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 1 0 1 0 0
Data V20VEN DC2EN XCLKEN TRIGEN V20VCLIMIT

NCN5121MNTWG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Communication ICs - Various KNXB
Lifecycle:
New from this manufacturer.
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