CY23FS04-2
Failsafe™ 2.5V/3.3V Zero Delay Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document Number: 38-07671 Rev. *B Revised January 29, 2010
Features
■
Internal DCXO for Continuous Glitch-free Operation
■
Zero Input-Output Propagation Delay
■
Low-Jitter (35 ps max RMS) Outputs
■
Low Output-to-Output Skew (200 ps max)
■
4.17 MHz to 50 MHz Reference Input
■
Supports Industry Standard Input Crystals
■
4.17 MHz to 50 MHz Outputs
■
5V-Tolerant Inputs
■
Phase-Locked Loop (PLL) Bypass Mode
■
Dual Reference Inputs
■
16-Pin TSSOP
■
2.5V or 3.3V Output Power Supplies
■
3.3V Core Power Supply
Functional Description
The CY23FS04-2 is a FailSafe™ zero delay buffer with two
reference clock inputs and four phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
The continuous, glitch-free operation is achieved by using a
DCXO, which serves as a redundant clock source in the event of
a reference clock failure by maintaining the last frequency and
phase information of the reference clock.
The unique feature of the CY23FS04-2 is that the DCXO is in fact
the primary clocking source, which is synchronized
(phase-aligned) to the external reference clock. When this
external clock is restored, the DCXO automatically resynchro-
nizes to the external clock.
The frequency of the crystal that is connected to the DCXO must
be an integer factor of the frequency of the reference clock. This
factor is set by two select lines: S[2:1], see Table 2. The output
power supply VDD can be connected to either 2.5V or 3.3V.
VDDC is the power supply pin for internal circuits and must be
connected to 3.3V.
CLKA[1:2]
CLKB[1:2]
DCXO
Decoder
2
Failsafe
TM
Block
PLL
XIN XOUT
2
2
REF2
FBK
S[2:1]
FAIL# /SAFE
REF1
REFSEL
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