Document Number: 38-07671 Rev. *B Page 4 of 12
FailSafe Function
The CY23FS04-2 is targeted at clock distribution applications
that require continued operation should the main reference clock
fail. Existing approaches to this requirement have used multiple
reference clocks with either internal or external methods to
switch between references. The problem with this technique is
that it leads to interruptions (or glitches) when transitioning from
one reference to another, often requiring complex external
circuitry or software to maintain system stability. The technique
implemented in this design completely eliminates any switching
of references to the PLL, greatly simplifying system design.
The CY23FS04-2 PLL is driven by the crystal oscillator, which is
phase-aligned to an external reference clock so that the output
of the device is effectively phase-aligned to the reference via the
external feedback loop. This is accomplished by using a digitally
controlled capacitor array to pull the crystal frequency over an
approximate range of +
300 ppm from its nominal frequency.
In this mode, if the reference frequency fails (stop or disappear),
the DCXO maintains its last setting and a flag signal
(FAIL#/SAFE) is set to indicate failure of the reference clock.
The CY23FS04-2 provides two select bits, S1 and S2, to control
the reference-to-crystal frequency ratio. The DCXO is internally
tuned to the phase and frequency of the external reference only
when the reference frequency divided by this ratio is within the
DCXO capture range. If the frequency is out of range, a flag is
set on the FAIL#/SAFE pin notifying the system that the selected
reference is not valid. If the reference moves in range, then the
flag is cleared, indicating to the system that the selected
reference is valid.
Figure 2. Fail#/Safe Timing for Input Reference Failing Catastrophically
Figure 3. Fail#/Safe Timing Formula
Table 3. FailSafe Timing Table
REF
OUT
Fail#/Safe
t
FSL
t
FSH
n
=
F
REF
F
XTAL
=4
(in above example)
t
FSL(max)
= 2 t
REF
x n
(
) +
25ns
t
FSH(min)
= 12 t
REF
x n
(
) +
25ns
Parameter Description Conditions Min Max Unit
t
FSL
Fail#/Safe Assert Delay Measured at 80% to 20%, Load = 15 pF See Figure 3 ns
t
FSH
Fail#/Safe Deassert Delay Measured at 80% to 20%, Load = 15 pF See Figure 3 ns
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