CY23FS04ZXC-2T

CY23FS04-2
Document Number: 38-07671 Rev. *B Page 10 of 12
Electrical Characteristics for FailSafe Devices
Parameter Description Test Conditions Min Typ Max Unit
V
IL
Input Low Voltage CMOS Levels, 30% of V
DD
0.3 × V
DD
V
V
IH
Input High Voltage CMOS Levels, 70% of V
DD
0.7 × V
DD
–V
I
IL
Input Low Current V
IN
= V
SS
(100k pull up only) 50 µA
I
IH
Input High Current V
IN
= V
DD
(100k pull down only) 50 µA
I
OL
Output Low Current V
OL
= 0.5V, V
DD
= 2.5V 18 mA
V
OL
= 0.5V, V
DD
= 3.3V 20 mA
I
OH
Output High Current V
OH
= V
DD
– 0.5V, V
DD
= 2.5V 18 mA
V
OH
= V
DD
– 0.5V, V
DD
= 3.3V 20 mA
I
DDQ
Quiescent Current All inputs grounded, PLL and DCXO in bypass
mode, Reference Input = 0
––250µA
Switching Characteristics for FailSafe Devices
Parameter
[7]
Description Test Conditions Min Max Unit
f
REF
Reference Frequency Commercial/Industrial Grades 4.17 50 MHz
f
OUT
Output Frequency 30 pF Load, Commercial Grade 4.17 50 MHz
f
XIN
DCXO Frequency 8.0 30 MHz
t
DC
Duty Cycle Measured at V
DD
/2 47 53 %
t
SR(I)
Input Slew Rate Measured on REF1 Input, 30% to 70% of V
DD
0.5 4.0 V/ns
t
SR(O)
Output Slew Rate Measured from 20% to 80% of V
DD
= 3.3V, 15 pF
Load
0.8 4.0 V/ns
Measured from 20% to 80% of V
DD
= 2.5V, 15 pF
Load
0.4 3.0 V/ns
t
SK(O)
Output to Output Skew All outputs equally loaded, measured at V
DD
/2 200 ps
t
SK(PP)
Part to Part Skew Measured at V
DD
/2 500 ps
t
(φ)
[6]
Static Phase Offset Measured at V
DD
/2 250 ps
t
D(φ)
[6]
Dynamic Phase Offset Measured at V
DD
/2 200 ps
t
J(CC)
Cycle-to-Cycle Jitter Load = 15 pF, f
OUT
6.25 MHz 200 ps
–35ps
RMS
Ordering Information
Part Number Package Type Product Flow
Pb-free
CY23FS04ZXC-2 16-Pin TSSOP Commercial, 0°C to 70°C
CY23FS04ZXC-2T 16-Pin TSSOP – Tape and Reel Commercial, 0°C to 70°C
Notes
6. The
t
(φ)
reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as
t
SR(I)
is maintained.
7. Parameters guaranteed by design and characterization, not 100% tested in production.
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CY23FS04-2
Document Number: 38-07671 Rev. *B Page 11 of 12
Package Diagram
Figure 14. 16-Pin TSSOP 4.40 mm Body
4.90[0.193]
1.10[0.043] MAX.
0.65[0.025]
0.20[0.008]
0.05[0.002]
16
PIN 1 ID
6.50[0.256]
SEATING
PLANE
1
0.076[0.003]
6.25[0.246]
4.50[0.177]
4.30[0.169]
BSC.
5.10[0.200]
0.15[0.006]
0.19[0.007]
0.30[0.012]
0.09[[0.003]
BSC
0.25[0.010]
0°-8°
0.70[0.027]
0.50[0.020]
0.95[0.037]
0.85[0.033]
PLANE
GAUGE
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05gms
51-85091 *B
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Document Number: 38-07671 Rev. *B Revised January 29, 2010 Page 12 of 12
FailSafe™ is a trademark of Cypress Semiconductor Corporation. Purchase of I
2
C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I
2
C
Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors
has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.
CY23FS04-2
© Cypress Semiconductor Corporation, 2003-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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the express written permission of Cypress.
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Document Title: CY23FS04-2 Failsafe™ 2.5V/3.3V Zero Delay Buffer
Document Number: 38-07671
Rev. ECN No.
Submission
Date
Orig. of
Change
Description of Change
** 224423 See ECN RGL New data sheet
*A 276753 See ECN RGL/ZJX Removed (T
LOCK
) Lock Time Specification
*B 2865337 01/25/2010 CXQ Updated format.
Added “Contents” section on page 2.
Removed previous Figures 5 and 6.
Added / separated Figures 7 through 12.
Changed references of “Cl” to “C
LOAD
”.
Removed extra T
A
reference in Absolute Maximum Conditions.
Removed industrial temperature range from T
A
.
Removed C
L
spec for f
OUT
> 100 MHz (f
OUT
max is 50 MHz for -2 devices).
Changed table captions for Tables 4, 5, and 6 to section headings.
Removed note 5 regarding programming cap array.
Replaced crystal ECX–5806–18.432M with ECX–6362–18.432M in Note 6.
Changed test condition from 15 pF to 30 pF for f
OUT
spec.
Removed industrial temp range devices from Ordering Information.
Removed unreferenced Note 9.
Updated package drawing specification to rev *B.
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CY23FS04ZXC-2T

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 3.3V 170MHz COM
Lifecycle:
New from this manufacturer.
Delivery:
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