8–6 Altera Corporation
September 2008
HardCopy Series Handbook, Volume 1
HardCopy APEX device can be prepared for operation after power up:
instant on, instant on after 50 ms, and configuration emulation. Each
mode is described below.
■ In instant on mode, the HardCopy APEX device is available for use
shortly after the device receives power. The on-chip power-on-reset
(POR) circuit will set or reset all registers. The CONF_DONE output
will be tri-stated once the power-on reset has elapsed. No
configuration device or configuration input signals are necessary.
■ In instant on after 50 ms mode, the HardCopy APEX device performs
in a similar fashion to the Instant On mode, except that there is an
additional delay of 50 ms (nominal), during which time the device is
held in reset stage. The CONF_DONE output is pulled low during this
time and then tri-stated after the 50 ms have elapsed. No
configuration devices or configuration input signals are necessary
for this option.
■ In configuration emulation mode, the HardCopy APEX device
undergoes an emulation of a full configuration sequence as if
configured by an external processor or an EPC device. In this mode,
the CONF_DONE signal is tri-stated after the correct number of clock
cycles. This mode may be useful where there is some dependency on
the configuration sequence (for example, multi-device configuration
or processor initialization). In this mode, the device expects to see all
configuration control and data input signals.
Speed Grades
Because HardCopy APEX devices are customized, no speed grading is
performed. All HardCopy APEX devices will meet the timing
requirements of the original FPGA of the fastest speed grade. Generally,
HardCopy APEX devices will have a higher f
MAX
than the corresponding
FPGA, but the speed increase will vary on a design-by-design basis.
Quartus II-
Generated
Output Files
The HardCopy migration process requires several Quartus II
software-generated files. These key output files are listed and explained
below.
■ The SRAM Object File (.sof) contains all of the necessary information
needed to configure a FPGA
■ The Compiler Report File (.csf.rpt) is parsed to extract useful
information about the design
■ The Verilog atom-based netlist file (.vo) is used to check the
HardCopy netlist
■ The pin out information file (.pin) contains user signal names and
I/O configuration information
