Altera Corporation 10–13
September 2008
Recommended Operating Conditions
Figure 10–2 shows the timing model for bidirectional I/O pin timing.
Figure 10–2. Synchronous Bidirectional Pin External Timing
Tables 10–21 and 10–22 describe HardCopy APEX device external timing
parameters.
PRN
CLRN
DQ
PRN
CLRN
DQ
IOE Register
Bidirectional Pin
Dedicated
Clock
PRN
CLRN
DQ
OE Register
Output IOE Register
Input Register
XZBIDIR
ZXBIDIR
t
t
INSUBIDIR
INHBIDIR
t
t
OUTCOBIDIR
t
Table 10–21. HardCopy APEX Device External Timing Parameters Note (1)
Symbol Clock Parameter Conditions
t
INSU
Setup time with global clock at IOE register
t
INH
Hold time with global clock at IOE register
t
OUTCO
Clock-to-output delay with global clock at IOE output register C1 = 35 pF
t
INSUPLL
Setup time with PLL clock at IOE input register
t
INHPLL
Hold time with PLL clock at IOE input register
t
OUTCOPLL
Clock-to-output delay with PLL clock at IOE output register C1 = 35 pF
Table 10–22. HardCopy APEX Device External Bidirectional Timing Parameters (Part 1 of 2) Note (1)
Symbol Parameter Condition
t
INSUBIDIR
Setup time for bidirectional pins with global clock at LAB-adjacent input
register
t
INHBIDIR
Hold time for bidirectional pins with global clock at LAB-adjacent input
register
t
OUTCOBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE
register
C1 = 35 pF
t
XZBIDIR
Synchronous output enable register to output buffer disable delay C1 = 35 pF
