Altera Corporation 9–3
September 2008
Document Revision History
Table 9–4 shows the JTAG timing parameters and values for HardCopy
devices.
f For more information about using JTAG BST circuitry in Altera devices,
refer to Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
in Altera Devices.
Document
Revision History
Table 9–5 shows the revision history for this chapter.
Table 9–4. HardCopy APEX JTAG Timing Parameters and Values
Symbol Parameter Min Max Unit
t
JCP
TCK clock period 100 ns
t
JCH
TCK clock high time
50 ns
t
JCL
TCK clock low time
50 ns
t
JPSU
JTAG port setup time 20 ns
t
JPH
JTAG port hold time 45 ns
t
JPCO
JTAG port clock to output 25 ns
t
JPZX
JTAG port high impedance to valid output 25 ns
t
JPXZ
JTAG port valid output to high impedance 25 ns
t
JSSU
Capture register setup time 20 ns
t
JSH
Capture register hold time 45 ns
t
JSCO
Update register clock to output 35 ns
t
JSZX
Update register high impedance to valid output 35 ns
t
JSXZ
Update register valid output to high impedance 35 ns
Table 9–5. Document Revision History (Part 1 of 2)
Date and Document
Version
Changes Made Summary of Changes
September 2008,
v2.3
Updated chapter number and metadata. —
June 2007, v2.2 Minor text edits. —
December 2006
v2.1
Updated revision history. Updated revision history.
March 2006 Formerly chapter 11; no content change.
