IDT 89HPES12NT12G2 Datasheet
16 of 32 December 16, 2013
Figure 4 GPIO AC Timing Waveform
Signal Symbol
Reference
Edge
Min Max Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK Tper_16a none 50.0 ns See Figure 5.
Thigh_16a,
Tlow_16a
10.0 25.0 ns
JTAG_TMS
1
,
JTAG_TDI
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK rising 2.4 ns
Thld_16b 1.0 ns
JTAG_TDO Tdo_16c JTAG_TCK falling 20 ns
Tdz_16c
2
2.
The values for this symbol were determined by calculation, not by testing.
—20ns
JTAG_TRST_N Tpw_16d
2
none 25.0 ns
Table 14 JTAG AC Timing Characteristics
Tpw_13b
EXTCLK
GPIO (asynchronous input)
IDT 89HPES12NT12G2 Datasheet
17 of 32 December 16, 2013
Figure 5 JTAG AC Timing Waveform
Recommended Operating Temperature
Recommended Operating Supply Voltages — Commercial Temperature
Grade Temperature
Commercial 0C to +70C Ambient
Industrial -40C to +85C Ambient
Table 15 PES12NT12G2 Operating Temperatures
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes 3.125 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC
value.
PCI Express Analog Power 0.95 1.0 1.1 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 16 PES12NT12G2 Operating Voltages — Commercial Temperature
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
IDT 89HPES12NT12G2 Datasheet
18 of 32 December 16, 2013
Recommended Operating Supply Voltages — Industrial Temperature
Power-Up/Power-Down Sequence
During power supply ramp-up, V
DD
CORE must remain at least 1.0V below V
DD
I/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 16
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 16 (and also listed below).
Note 1: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be
reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in V
DD
PEA, V
DD
PEHA, and
V
DD
PETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turned-
off port is close to zero. For example, if 3 ports out of 16 are turned off, then the power savings for each of the above three power rails can be
calculated quite simply as 3/16 multiplied by the power consumption indicated in the above table.
Note 2: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: V
DD
PEA, V
DD
PEHA, and
V
DD
PETA.
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes 3.125 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC
value.
PCI Express Analog Power 0.95 1.0 1.05 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 17 PES12NT12G2 Operating Voltages — Industrial Temperature
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465
Typ
Power
Max
Power
x4/x4/x1/x1/x1/x1
(Full Swing)
mA 2241 3300 821 844 99 134 296 326 3 5
Watts 2.24 3.63 0.82 0.93 0.25 0.37 0.30 0.36 0.01 0.02 3.62 5.31
x4/x4/x1/x1/x1/x1
(Half Swing)
mA 2241 3300 706 726 99 134 154 170 3 5
Watts 2.24 3.63 0.71 0.80 0.25 0.37 0.16 0.19 0.01 .02 3.37 5.01
Table 18 PES12NT12G2 Power Consumption

89H12NT12G2ZCHLGI

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCIE SWITCH
Lifecycle:
New from this manufacturer.
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