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89H12NT12G2ZCHLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
IDT 89HPES12NT12G2 Datasheet
4 of 32 December 16, 2013
SMBus Interface
The PES12NT12G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES12NT12G2,
allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration
register values of the PES12NT12G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface
is also used by an external Hot-Plug I/O expander.
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
SSMBADDR2 pins. As shown in Figure 2, the master and slave SMBuses may only be used in a split configuration. In the split configuration, the
master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not
support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM
and I/O expander slaves.
Figure 2 Split SMBus Interface Configuration
Hot-Plug Interface
The PES12NT12G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES12NT12G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES12NT12G2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES12NT12G2. In response to an I/O expander interrupt, the PES12NT12G2 generates
an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES12NT12G2 provides 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus
slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES12NT12G2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Note: Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to lane 1, etc.
Processor
Switch
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
Hot-Plug
I/O
Expander
IDT 89HPES12NT12G2 Datasheet
5 of 32 December 16, 2013
Signal Type Name/Description
PE00RN[0]
PE00RP[0]
I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pair for
port 0.
PE00TN[0]
PE00TP[0]
O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for
port 0.
PE01RN[0]
PE01RP[0]
I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pair for
port 1.
PE01TN[0]
PE01TP[0]
O PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pair for
port 1.
PE02RN[0]
PE02RP[0]
I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pair for
port 2.
PE02TN[0]
PE02TP[0]
O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pair for
port 2.
PE03RN[0]
PE03RP[0]
I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for
port 3.
PE03TN[0]
PE03TP[0]
O PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for
port 3.
PE08RN[0]
PE08RP[0]
I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pair for
port 8.
PE08TN[0]
PE08TP[0]
O PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pair for
port 8.
PE09RN[0]
PE09RP[0]
I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pair for
port 9.
PE09TN[[0]
PE09TP[0]
O PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pair for
port 9.
PE10RN[0]
PE10RP[0]
I PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pair for
port 10.
PE10TN[0]
PE10TP[0]
O PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pair for
port 10.
PE11RN[0]
PE11RP[0]
I PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pair for
port 11.
PE11TN[0]
PE11TP[0]
O PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pair for
port 11.
PE16RN[0]
PE16RP[0]
I PCI Express Port 16 Serial Data Receive.
Differential PCI Express receive pair for
port 16.
PE16TN[0]
PE16TP[0]
O PCI Express Port 16 Serial Data Transmit. Differential PCI Express transmit pair for
port 16.
PE17RN[0]
PE17RP[0]
I PCI Express Port 17 Serial Data Receive. Differential PCI Express receive pair for
port 17.
PE17TN[0]
PE17TP[0]
O PCI Express Port 17 Serial Data Transmit. Differential PCI Express transmit pair for
port 17.
PE18RN[0]
PE18RP[0]
I PCI Express Port 18 Serial Data Receive. Differential PCI Express receive pair for
port 18.
Table 2 PCI Express Interface Pins (Part 1 of 2)
IDT 89HPES12NT12G2 Datasheet
6 of 32 December 16, 2013
PE18TN[0]
PE18TP[0]
O PCI Express Port 18 Serial Data Transmit. Differential PCI Express transmit pair for
port 18.
PE19RN[0]
PE19RP[0]
I PCI Express Port 19 Serial Data Receive. Differential PCI Express receive pair for
port 19.
PE19TN[0]
PE19TP[0]
O PCI Express Port 19 Serial Data Transmit. Differential PCI Express transmit pair for
port 19.
Signal Type Name/Description
GCLKN[1:0]
GCLKP[1:0]
I Global Reference Clock. Differential reference clock input pairs. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the device logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.
Note: Both pairs of the Global Reference Clocks must be connected to and
derived from the same clock source. Refer to the Overview section of
Chapter 2 in the PES12NT12G2 User Manual for additional details.
P08CLKN
P08CLKP
I Port Reference Clock. Differential reference clock pair associated with
port 8.
P16CLKN
P16CLKP
I Port Reference Clock. Differential reference clock pair associated with
port 16.
Table 3 Reference Clock Pins
Signal Type Name/Description
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the
master SMBus. It is active and generating the clock only when the EEPROM or I/O
Expanders are being accessed.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
SSMBADDR[2,1] I Slave SMBus Address. These pins determine the SMBus address to which the slave
SMBus interface responds.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the
slave SMBus.
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.
Table 4 SMBus Interface Pins
Signal Type Name/Description
Table 2 PCI Express Interface Pins (Part 2 of 2)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

89H12NT12G2ZCHLGI

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Description:
PCI Interface IC PCIE SWITCH
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