HIP2103, HIP2104
7
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November 27, 2013
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On Resistance R
Don
I
VDD-HB
= 75mA, HI = 0, LI = 1 8.2 2.42 15 Ω
LO GATE DRIVER
Sinking r
DS(ON)
RDS
LOL
I
LO
= 100mA, LI = 0 2.68 0.61 11 Ω
Sourcing r
DS(ON)
RDS
LOH
I
LO
= -75mA, HI = 1 6.47 2.3 15 Ω
Peak Pull-Up Current
I
LOH12
HI = 1
V
DD
= 12V, Cload = 1000pF
1A
I
LOH5
HI = 1
V
DD
= 5V, Cload = 1000pF
(HIP2103 only)
A
Peak Pull-Down Current
I
LOL12
HI = 0
V
DD
= 12V, Cload = 1000pF
2A
I
LOL5
HI = 0
V
DD
= 5V, Cload = 1000pF
(HIP2103 only)
A
HO GATE DRIVER
Sinking r
DS(ON)
RDS
HOL
I
HO
= 100mA, HI = 0 6.1 4.4 11 Ω
Sourcing r
DS(ON)
RDS
HOH
I
HO
= -100mA, HI = 1 11.9 9.7 15 Ω
Peak Pull-Up Current
I
HOH12
HI = 1
V
DD
= 12V, Cload = 1000pF
1A
I
HOH5
HI = 1
V
DD
= 5V, Cload = 1000pF
(HIP2103 only)
1A
Peak Pull-Down Current
I
HOL12
HI = 0
V
DD
= 12V, Cload = 1000pF
2A
I
HOL5
HI = 0
V
DD
= 5V, Cload = 1000pF
(HIP2103 only)
A
NOTES:
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
13. The UV lockout does not disable the V
DD
and V
CC
outputs.
DC Electrical Specifications V
DD
= V
HB
= 12V (for HIP2103), V
SS
= V
HS
= 0V, V
BAT
= 18V (for HIP2104), LI = HI = 0V. No load on HO
and LO unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C T
J
= -40°C to +125°C
UNITSMIN TYP MAX
MIN
(Note 12)
MAX
(Note 12)
HIP2103, HIP2104
8
FN8276.0
November 27, 2013
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AC Electrical Specifications V
DD
= 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. V
DD
load = 1µF and V
CC
load = 1µF (HIP2104 only) Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C T
J
= -40°C to +125°C
UNITSMIN TYP MAX MIN MAX
VDen and VCen Turn-On Delay
(Figure 5) (HIP2104 only)
t
Den
t
Cen
VDen = VCen = 1,
V
CC
= V
DD
= 10%,
V
BAT
= 50V
1.69 1.0 2.5 ms
VDen and VCen Turn-on Delay
(Figure 5) (HIP2104 only)
t
Den
t
Cen
VDen = VCen = 1,
V
CC
= V
DD
= 10%,
V
BAT
= 18V
1.68 1.1 2.54 ms
VDen and VCen Turn-on Delay Matching
(Figure 5) (VDen - VCen) (HIP2104 only)
t
VenM
VDen = VCen = 1,
V
CC
= 10%, V
DD
= 10%
V
BAT
= 50V
40 -290 340 ns
VDen and VCen Turn-on Delay Matching
(Figure 5) (VDen - VCen) (HIP2104 only)
t
VenM
VDen = VCen = 1,
V
CC
= 10%, V
DD
= 10%
V
BAT
= 18V
40 -290 350 ns
LO Turn-Off Propagation Delay
(LI to LO falling) (Figure 6)
t
FL12
HI = 0, LI = 1 to 0
V
DD
= 12V
27 13 39 ns
t
FL5
HI = 0, LI = 1 to 0
V
DD
= 5V (HIP2103 only)
30 23 46 ns
HO Turn-Off Propagation Delay
(HI to HO falling) (Figure 6)
t
FH12
LI = 0, HI = 1 to 0
V
DD
= 12V
23 10 35 ns
t
FH5
LI = 0, HI = 1 to 0
Vv = 5V (HIP2103 only)
27 19 38 ns
LO Turn-On Propagation Delay
(LI to LO rising) (Figure 6)
t
RL12
HI = 0, LI = 0 to 1
V
DD
= 12V
21 732ns
t
RL5
HI = 0, LI = 0 to 1
V
DD
= 5V (HIP2103 only)
25 12 37 ns
HO Turn-On Propagation Delay
(HI to HO rising) (Figure 6)
t
RH12
LI = 0, HI = 0 to 1
V
DD
= 12V
23 935ns
t
RH5
LI = 0, HI = 0 to 1
V
DD
= 5V (HIP2103 only)
28 15 40 ns
Turn-On/Off Propagation Mismatch
(HO rising to LO falling) (Figure 6)
t
MONHL
LI = 1 -> 0
HI = 0 -> 1
-2.5 -8 +3 ns
Turn-On/Off Propagation Mismatch
(LO rising to HO falling) (Figure 6)
t
MONLH
HI = 1 -> 0
LI = 0 -> 1
-4.2 -9.0 +5.4 ns
LO Output Rise Time
(10% to 90% )
t
R12
CL = 1nF
V
DD
= 12V
20.5 735ns
t
R5
CL = 1nF
V
DD
= 5V (HIP2103 only)
19.5 632ns
HO Output Rise Time
(10% to 90%)
t
R12
CL = 1nF
V
DD
= 12V
21 835ns
t
R5
CL = 1nF
V
DD
= 5V (HIP2103 only)
21 834ns
LO Output Fall Time
(90% to 10%)
t
F12
CL = 1nF
V
DD
= 12V
17 330ns
t
F5
CL = 1nF
V
DD
= 5V (HIP2103 only)
17 330ns
HO Output Fall Time
(90% to 10%)
t
F12
CL = 1nF
V
DD
= 12V
16 230ns
t
F5
CL = 1nF
V
DD
= 5V (HIP2103 only)
16 1.5 29 ns
HIP2103, HIP2104
9
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November 27, 2013
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Time Delay to Set Sleep Mode
(Note 14, Figure 4)
t
SlpS
HI = LI = 0 -> 1 17 927µs
Time Delay to Reset Sleep Mode
(Note 14, Figure 4)
t
SlpR
HI = 0, LI = 0 -> 1 17 927µs
NOTE:
14. When HI and LI are on simultaneously, HO and LO are never on simultaneously. This feature is intended to initiate sleep. This feature cannot be used
to prevent shoot-through for normal alternating switching between LI and HI. Dead time must be provided when HI = 0 -> LI = 1, or LI = 0 -> HI = 1.
See Timing Diagrams (Figure 4).
AC Electrical Specifications V
DD
= 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. V
DD
load = 1µF and V
CC
load = 1µF (HIP2104 only) Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C T
J
= -40°C to +125°C
UNITSMIN TYP MAX MIN MAX
Timing Diagrams
FIGURE 3. VDD POWER-ON/OFF TIMING FOR SLEEP MODE
2M to HS2M to HS
100 to LS100 to LS
HO = Logic inputs
LO = Logic inputs
~
~
~
~
~
~
~
~
UV threshold
HO
LO
*SLEEP
UVLO
VDD
VDen
VCC
VCen
HO
LO
*SLEEP
UVLO
VDD
VDen
VCC
VCen
~
~
~
~
t
VCen
t
VDen
t
SlpS
t
SlpR
(Vden and VCen apply to HIP2104 only)
*Sleep is an internal state. Minimal IDD or IBAT current results when active (high).

HIP2104FRAANZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 1/2 Bridge Driver with 4V UVLO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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