Data Sheet ADuM140D/ADuM140E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Supply Current per Channel
Quiescent Input I
DDI (Q)
0.3 0.53 mA V
I
4
= 0 (E0, D0), 1 (E1, D1)
5
Quiescent Output I
DDO (Q)
0.5 0.67 mA V
I
4
= 0 (E0, D0), 1 (E1, D1)
5
Quiescent Input I
DDI (Q)
3.0 4.9 mA V
I
4
= 1 (E0, D0), 0 (E1, D1)
5
DDO (Q)
I
4
5
Dynamic Input I
DDI (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output I
DDO (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive V
DDx
Threshold V
DDxUV+
1.6 V
Negative V
DDx
Threshold V
DDxUV−
1.5 V
V
DDx
Hysteresis V
DDxUVH
0.1 V
AC SPECIFICATIONS
Output Rise/Fall Time t
R
/t
F
2.5 ns 10% to 90%
Common-Mode Transient Immunity
6
H
Ix
DDx
CM
transient magnitude = 800 V
|CM
L
| 75 100 kV/µs V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
1
I
Ox
is the Channel x output current, where x = A, B, C, or D.
2
V
IxH
is the input side logic high.
3
V
IxL
is the input side logic low.
4
V
I
is the voltage input.
5
E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section.
6
|CM
H
| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V
O
) > 0.8 V
DDx
. |CM
L
| is the maximum common-
mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Table 4. Total Supply Current vs. Data Throughput
1 Mbps 25 Mbps 100 Mbps
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Supply Current Side 1 I
DD1
6.6 9.8 7.4 11.2 10.7 15.9 mA
Supply Current Side 2 I
DD2
2.0 3.7 3.5 5.5 8.2 11.6 mA
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 2.5 V. Minimum/maximum specifications apply over the entire recommended
operation range: 2.25 V ≤ V
DD1
≤ 2.75 V, 2.25 V ≤ V
DD2
≤ 2.75 V, −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching specifications
are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate 150 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
5.0 7.0 14 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew t
PSK
6.8 ns Between any two units at the
same temperature, voltage, load
Channel Matching
Codirectional t
PSKCD
0.7 3.0 ns
Opposing Direction t
PSKOD
0.7 3.0 ns
Jitter 800 ps p-p See the Jitter Measurement section
Rev. 0 | Page 5 of 18
