Data Sheet ADuM140D/ADuM140E
ELECTRICAL CHARACTERISTICS—1.8 V OPERATION
All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 1.8 V. Minimum/maximum specifications apply over the entire recommended
operation range: 1.7 V ≤ V
DD1
≤ 1.9 V, 1.7 V ≤ V
DD2
≤ 1.9 V, and −40°C ≤ T
A
≤ +125°C, unless otherwise noted. Switching specifications
are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width PW 6.6 ns Within PWD limit
Data Rate 150 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
5.8 8.7 15 ns 50% input to 50% output
Pulse Width Distortion PWD 0.7 3 ns |t
PLH
− t
PHL
|
Change vs. Temperature 1.5 ps/°C
Propagation Delay Skew t
PSK
7.0 ns Between any two units at the same
temperature, voltage, and load
Channel Matching
PSKCD
Opposing Direction t
PSKOD
0.7 3.0 ns
Jitter 470 ps p-p See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold
Logic High V
IH
0.7 × V
DDx
V
Logic Low V
IL
0.3 × V
DDx
V
Output Voltage
Logic High V
OH
V
DDx
− 0.1 V
DDx
V I
Ox
1
= −20 µA, V
Ix
= V
IxH
2
V
DDx
− 0.4 V
DDx
− 0.2 V I
Ox
1
= −2 mA, V
Ix
= V
IxH
2
Logic Low V
OL
0.0 0.1 V I
Ox
1
= 20 µA, V
Ix
= V
IxL
3
0.2 0.4 V I
Ox
1
= 2 mA, V
Ix
= V
IxL
3
Input Current per Channel I
I
−10 +0.01 +10 µA 0 V ≤ V
Ix
≤ V
DDx
V
E2
Enable Input Pull-Up Current I
PU
−10 −3 µA V
E2
= 0 V
1
PD
1
DDx
Tristate Output Current per Channel I
OZ
−10 +0.01 +10 µA 0 V ≤ V
Ox
≤ V
DDx
Supply Current per Channel
Quiescent Input I
DDI (Q)
0.3 0.48 mA V
I
4
= 0 (E0, D0), 1 (E1, D1)
5
Quiescent Output I
DDO (Q)
0.5 0.66 mA V
I
4
= 0 (E0, D0), 1 (E1, D1)
5
Quiescent Input I
DDI (Q)
3.0 4.9 mA V
I
4
= 1 (E0, D0), 0 (E1, D1)
5
Quiescent Output I
DDO (Q)
0.5 0.69 mA V
I
4
= 1 (E0, D0), 0 (E1, D1)
5
Dynamic Input I
DDI (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
Dynamic Output I
DDO (D)
0.01 mA/Mbps Inputs switching, 50% duty cycle
Undervoltage Lockout UVLO
Positive V
DDx
Threshold V
DDxUV+
1.6 V
Negative V
DDx
Threshold V
DDxUV−
1.5 V
V
DDx
Hysteresis V
DDxUVH
0.1 V
AC SPECIFICATIONS
R
F
Common-Mode Transient Immunity
6
|CM
H
| 75 100 kV/µs V
Ix
= V
DDx
, V
CM
= 1000 V,
transient magnitude = 800 V
|CM
L
| 75 100 kV/µs V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
1
I
Ox
is the Channel x output current, where x = A, B, C, or D.
2
V
IxH
is the input side logic high.
3
V
IxL
is the input side logic low.
4
V
I
is the voltage input.
5
E0 is the ADuM140E0 model, D0 is the ADuM140D0 model, E1 is the ADuM140E1 model, and D1 is the ADuM140D1 model. See the Ordering Guide section.
6
|CM
H
| is the maximum common-mode voltage slew rate that can be sustained while maintaining the voltage output (V
O
) > 0.8 V
DDx
. |CM
L
| is the maximum common-
mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode
voltage edges.
Rev. 0 | Page 7 of 18
