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ADA4930-1YCPZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet ADA4930-1/ADA4930-2
Rev. B | Page 19 of 25
MINIMUM R
G
VALUE
Due to the wide bandwidth of the ADA4930-1/ADA4930-2, the
value of R
G
must be greater than or equal to 301 Ω at unity gain
to provide sufficient damping in the amplifier front end. In the
terminated case, R
G
includes the Thevenin resistance of the
source and load terminations.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The V
OCM
pin of the ADA4930-1/ADA4930-2 is biased at 3/10 of
the total supply voltage above −V
S
with an internal voltage divider.
The input impedance of the V
OCM
pin is 8.4 kΩ. When relying
on the internal bias, the output common-mode voltage is within
about 100 mV of the expected value.
In cases where accurate control of the output common-mode
level is required, it is recommended that an external source or
resistor divider be used with source resistance less than 100 Ω.
The output common-mode offset listed in the Specifications
section assumes that the V
OCM
input is driven by a low impedance
voltage source.
It is also possible to connect the V
OCM
input to a common-mode
voltage (V
CM
) output of an ADC. However, care must be taken
to ensure that the output has sufficient drive capability. The
input impedance of the V
OCM
pin is approximately 10 kΩ. If
multiple ADA4930-1/ADA4930-2 devices share one reference
output, it is recommended that a buffer be used.
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
The effective input impedance depends on whether the signal
source is single-ended or differential. For a balanced differential
input signal, as shown in Figure 44, the input impedance (R
IN, dm
)
between the inputs (+D
IN
and −D
IN
) is R
IN, dm
= 2 × R
G
.
+V
S
ADA4930
+IN
–IN
R
F
R
F
+D
IN
–D
IN
V
OCM
R
G
R
G
V
OUT, dm
09209-051
Figure 44. ADA4930-1/ADA4930-2 Configured for Balanced (Differential) Inputs
For an unbalanced single-ended input signal, as shown in
Figure 45, the input impedance is
R
IN,SE
= R
G1
)1(
β2β1
β2β1
where:
β1 =
F1
G1
G1
RR
R
β2 =
2
2
F
G2
G
RR
R
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
R
G1
R
G2
R
F2
R
F1
V
OCM
R
IN, SE
0
9209-052
Figure 45. ADA4930-1/ADA4930-2 with Unbalanced (Single-Ended) Input
For a balanced system where R
G1
= R
G2
= R
G
and R
F1
= R
F2
= R
F
,
the equations simplify to
)2(
1
F
G
F
G
IN,SE
F
G
G
RR
R
R
Rand
RR
R
β2β1
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor R
G1
. The common-mode
voltage at the amplifier input terminals can be easily determined
by noting that the voltage at the inverting input is equal to the
noninverting output voltage divided down by the voltage divider
formed by R
F2
and R
G2
. This voltage is present at both input
terminals due to negative voltage feedback and is in phase with
the input signal, thus reducing the effective voltage across R
G1
,
partially bootstrapping it.
ADA4930-1/ADA4930-2 Data Sheet
Rev. B | Page 20 of 25
Terminating a Single-Ended Input
This section describes the five steps that properly terminate a
single-ended input to the ADA4930-1/ADA4930-2. Assume a
system gain of 1, R
F1
= R
F2
= 301 Ω, an input source with an open-
circuit output voltage of 2 V p-p, and a source resistance of 50 Ω.
Figure 46 shows this circuit.
1.
Calculate the input impedance.
β1 = β2 = 301/602 = 0.5 and R
IN
= 401.333 Ω
R
S
50
V
S
2V p-p
R
IN
401.333
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
R
G1
301
R
G2
301
R
F2
301
R
F1
301
V
OCM
09209-053
Figure 46. Single-Ended Input Impedance R
IN
2. Add a termination resistor, R
T
. To match the 50 Ω source
resistance, R
T
is added. Because R
T
||401.33 Ω = 50 Ω,
R
T
= 57.116 .
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
R
S
50
R
G1
301
R
G2
301
R
F2
301
R
F1
301
V
OCM
V
S
2V p-p
R
IN
50
R
T
57.116
0
9209-054
Figure 47. Adding Termination Resistor R
T
3. Replace the source-termination resistor combination with
its Thevenin equivalent. The Thevenin equivalent of the
source resistance R
S
and the termination resistance R
T
is
R
TH
= R
S
||R
T
= 26.66 . The Thevenin equivalent of the
source voltage is
V
TH
= V
S
T
S
T
RR
R
= 1.066 V p-p
R
S
50
V
S
2
V p-
p
R
T
57.116
R
TH
26.661
V
TH
1.066V p-p
0
9209-055
Figure 48. Thevenin Equivalent Circuit
4.
Set R
F1
= R
F2
= R
F
to maintain a balanced system.
Compensate the imbalance caused by R
TH
. There are two
methods available to compensate, which follow:
Add R
TH
to R
G2
to maintain balanced gain resistances
and increase R
F1
and R
F2
to R
F
=
TH
S
V
V
Gain(R
G
+ R
TH
) to
maintain the system gain.
Decrease R
G2
to R
G2
=
GainV
VR
S
TH
F
to maintain system
gain and decrease R
G1
to (R
G2
− R
TH
) to maintain
balanced gain resistances.
The first compensation method is used in the Analog Devices
DiffAmpCalc™ tool. Using the second compensation method,
R
G2
= 160.498 Ω and R
G1
= 160.498 − 26.66 = 133.837 . The
modified circuit is shown in Figure 49.
ADA4930
R
L
V
OUT, dm
+V
S
–V
S
R
TH
26.661
R
G1
133.837
R
G2
160.498
R
F2
301
R
F1
301
V
OCM
V
TH
1.066V p-p
09209-056
Figure 49. Thevenin Equivalent with Matched Gain Resistors
Figure 49 presents an easily manageable circuit with matched
feedback loops that can be easily evaluated.
5. The modified gain resistor, R
G1
, changes the input impedance.
Repeat Step 1 through Step 4 several times using the modified
value of R
G1
from the previous iteration until the value of
R
T
does not change from the previous iteration. After three
additional iterations, the change in R
G1
is less than 0.1%.
The final circuit is shown in Figure 50 with the closest
0.5% resistor values.
ADA4930
R
L
V
OUT, dm
1.990V p-p
+V
S
–V
S
R
S
50
R
G
142
V
P
V
N
R
G2
169
R
F1
301
R
F2
301
V
OCM
V
S
2V p-p
0.998V p-p
R
T
64.2
09209-057
Figure 50. Terminated Single-Ended-to-Differential System with G = 1
Data Sheet ADA4930-1/ADA4930-2
Rev. B | Page 21 of 25
Terminating a Single-Ended Input in a Single-Supply
Applications
When the application circuit of Figure 50 is powered by a single
supply, the common-mode voltage at the amplifier inputs, V
P
and V
N
, may have to be raised to comply with the specified input
common-mode range. Two methods are available: a dc bias on
the source, as shown in Figure 51, or by connecting resistors
R
CM
between each input and the supply, as shown on Figure 54.
Input Common-Mode Adjustment with DC Biased Source
To drive a 1.8 V ADC with V
CM
= 1 V, a 3.3 V single supply
minimizes the power dissipation of the ADA4930-1/ADA4930-2.
The application circuit of Figure 50 on a 3.3 V single supply with a
dc bias added to the source is shown in Figure 51.
ADA4930
R
L
V
OUT, dm
1.990V p-p
3.3V
R
S
50
R
G1
142
V
P
V
N
R
G2
142
R
F2
301
R
F1
301
V
OCM
V
S
2V p-p
V
DC
R
T
64.2
64.2
50
09209-151
Figure 51. Single-Supply, Terminated Single-Ended-to-Differential System
with G = 1
To determine the minimum required dc bias, the following steps
must be taken:
1.
Convert the terminated inputs to their Thevenin equivalents,
as shown in the Figure 52 circuit.
ADA4930
R
L
V
OUT, dm
1.99V p-p
3.3V
VON
VOP
R
TH
28.11
R
G1
142
V
P
V
N
R
G2
142
R
F2
301
R
F1
301
V
OCM
V
TH
1.124V p-p
V
DC-TH
0
9209-159
R
TH
28.11
Figure 52. Thevenin Equivalent of Single-Supply Application Circuit
2. Write a nodal equation for V
P
or V
N
.

THDCTH
ON
THDCTH
P
VVVVVV
28.11142301
301
OP
THDC
N
VVV
28.11142301
301
Recognize that while the ADA4930-1/ADA4930-2 is in its
linear operating region, V
P
and V
N
are equal. Therefore,
both equations in Step 2 give equal results.
3.
To comply with the minimum specified input common-mode
voltage of 0.3 V at V
S
= 3.3 V, set the minimum value of V
P
and V
N
to 0.3 V.
4.
Recognize that V
P
and V
N
are at their minimum values when
V
OP
and V
S
are at their minimum (and therefore V
ON
is at its
maximum).
Let
V
P min
= V
N min
= 0.3 V, V
OCM
= V
CM
= 1 V, V
TH min
= −V
TH
/2
V
ON max
= V
OCM
+ V
OUT, dm
/4 and V
OP min
= V
OCM
− V
OUT, dm
/4
Substitute conditions into the nodal equation for V
P
and solve
for V
DC-TH
.
0.3 = −1.124/2 + V
DC-TH
+ 0.361 × (1 + 1.99/4 = 1.124/2 – V
DC-TH
)
0.3 + 0.562 − 0.361 − 0.18 − 0.203 = 0.639 V
DC-TH
V
DC-TH
= 0.186 V
Or
Substitute conditions into the nodal equation for V
N
and
solve for V
DC-TH
.
0.3 = V
DC-TH
+ 0.361 × (1 − 1.99/4 − V
DC-TH
)
0.3 – 0.361 + 0.18 = 0.639 × V
DC-TH
V
DC-TH
= 0.186 V
5.
Converting VDC-TH from its Thevenin equivalent results in
V 0.330.186
TH
TH
S
DC
R
RR
V
The final application circuit is shown in Figure 53. The
additional dc bias of 0.33 V at the inputs ensures that the
minimum input common-mode requirements are met when
the source signal is bipolar with a 2 V p-p amplitude and
V
OCM
is at 1 V.
3.3V
ADA4930
R
L
V
OUT, dm
1.990V p-p
R
S
50
R
G1
142
R
G2
142
R
F2
301
R
F1
301
V
OCM
V
S
2V p-p
R
T
64.2
64.2
09209-160
V
P
V
N
50
V
DC
0.33V
Figure 53. Single-Supply Application Circuit with DC Source Bias
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ADA4930-1YCPZ-R7

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Manufacturer:
Analog Devices Inc.
Description:
Differential Amplifiers Ultralow Noise Dvrs for Low VTG ADC's
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