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74LVC32AD-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
74LVC32A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 28 February 2013 9 of 15
NXP Semiconductors
74LVC32A-Q100
Quad 2-input OR gate
Fig 9. Package outline SOT337-1 (SSOP14)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65 1.25 0.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1
99-12-27
03-02-19
(1)
w M
b
p
D
H
E
E
Z
e
c
v M
A
X
A
y
1
7
14
8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
A
max.
2
74LVC32A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 28 February 2013 10 of 15
NXP Semiconductors
74LVC32A-Q100
Quad 2-input OR gate
Fig 10. Package outline SOT402-1 (TSSOP14)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153
99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
17
14
8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
A
max.
1.1
pin 1 index
74LVC32A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 28 February 2013 11 of 15
NXP Semiconductors
74LVC32A-Q100
Quad 2-input OR gate
Fig 11. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A
1
E
h
b
UNIT
ye
0.2
c
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
3.1
2.9
D
h
1.65
1.35
y
1
2.6
2.4
1.15
0.85
e
1
2
0.30
0.18
0.05
0.00
0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A
(1)
max.
A
A
1
c
detail X
y
y
1
C
e
L
E
h
D
h
e
e
1
b
26
13
9
8
7
1
14
X
D
E
C
B
A
02-10-17
03-01-27
terminal 1
index area
AC
C
B
v
M
w
M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

74LVC32AD-Q100J

Mfr. #:
Buy 74LVC32AD-Q100J
Manufacturer:
Nexperia
Description:
Logic Gates 74LVC32AD-Q100/SO14/REEL 13" Q
Lifecycle:
New from this manufacturer.
Delivery:
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