74LVC32A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 28 February 2013 3 of 15
NXP Semiconductors
74LVC32A-Q100
Quad 2-input OR gate
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14
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Table 2. Pin description
Symbol Pin Description
1A, 2A, 3A, 4A 1, 4, 9, 12 data input
1B, 2B, 3B, 4B 2, 5, 10, 13 data input
1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function selection
[1]
Input Output
nA nB nY
LLL
XHH
HXH