AD7398/AD7399
Rev. C | Page 16 of 24
POWER-ON RESET
When the V
DD
power supply is turned on, an internal reset
strobe forces all the input and DAC registers to the zero-code
state. The V
DD
power supply should have a smooth positive
ramp without drooping in order to have consistent results,
especially in the region of V
DD
= 1.5 V to 2.2 V. The V
SS
supply
has no effect on the power-on reset performance. The DAC
register data stays at zero until a valid serial register data load
takes place.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and V
DD
as shown in Figure 28.
02179-028
GND
V
DD
DIGITAL INPUTS
5kΩ
Figure 28. Equivalent ESD Protection Circuits
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7398/AD7399 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal, and a synchronization signal. The AD7398/AD7399
require a 16-bit/14-bit data word with data valid on the rising edge
of CLK. The DAC update can be done automatically when all the
data is clocked in, or it can be done under control of
LDAC
.
ADSP-2101 to AD7398/AD7399 Interface
Figure 29 shows a serial interface between the AD7398/AD7399
and the ADSP-2101. The ADSP-2101 is set to operate in the serial
port (SPORT) transmit alternate framing mode. The ADSP-2101 is
programmed through the SPORT control register and should be
configured as follows: Internal clock operation, active low framing,
16-bit-word length. For the AD7398, transmission is initiated by
writing a word to the Tx register after the SPORT has been
enabled. For the AD7399, the first two bits are don’t care as the
AD7399 keeps the last 14 bits. Similarly, transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. Because of the edge-triggered difference, an inverter is
required at the SCLKs between the DSP and the DAC.
02179-029
AD7398/
AD7399
ADSP-2101
1
FO LDAC
TFS CS
DT SDI
SCLK CLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. ADSP-2101 to AD7398/AD7399 Interface
68HC11/68L11 to AD7398/AD7399 Interface
Figure 30 shows a serial interface between the AD7398/AD7399
and the 68HC11/68L11 microcontroller. SCK of the 68HC11/
68L11 drives the CLK of the DAC, and the MOSI output drives the
serial data lines SDI.
CS
signal is driven from one of the port lines.
The 68HC11/68L11 are configured for master mode; MSTR = 1,
CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is
valid on the rising edge of SCK.
02179-030
AD7398/
AD7399
68HC11/
68L11
1
PC6 LDAC
PC7 CS
MOS1 SDI
SCK CLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 30. 68HC11/68L11 to AD7398/AD7399 Interface
MICROWIRE™ to AD7398/AD7399 Interface
Figure 31 shows an interface between the AD7398/AD7399 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD7398/
AD7399 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
02179-031
AD7398/
AD7399
MICROWIRE
1
SO SDI
SCK CLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
CS CS
Figure 31. MICROWIRE to AD7398/AD7399 Interface
80C51/80L51 to AD7398/AD7399 Interface
A serial interface between the AD7398/AD7399 and the 80C51/
80L51 microcontroller is shown in Figure 32
. TxD of the micro-
controller drives the CLK of the AD7398/AD7399, and RxD drives
the serial data line of the DAC. P3.3 is a bit-programmable pin on
the serial port that is used to drive
CS
.
02179-032
AD7398/
AD7399
80C51/
80L51
1
P3.4
LDAC
P3.3
CS
RxD
SDI
TxD CLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 32. 80C51/80L51 to AD7398/AD7399 Interface
