OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7399BRZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
AD7398/AD7399
Rev. C | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
02179-005
1
V
OUT
B
16
V
OUT
C
2
V
OUT
A
15
V
OUT
D
3
V
SS
14
V
DD
4
V
REF
A
13
V
REF
C
5
V
REF
B
12
V
REF
D
6
GND
11
SDI
7
LDAC
10
CLK
8
RS
9
CS
AD7398/
AD7399
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Table 5. Control Logic Truth Table
CS
CLK
LDAC
Serial Shift Register Function Input Register Function DAC Register
H X H No effect No effect No effect
L L H No effect No effect No effect
L
↑+
H Shift register data advanced one bit Latched No effect
L H H No effect Latched No effect
↑+
L/H H No effect Updated with shift register contents No effect
H X L No effect Latched Transparent
H X
↑+
No effect Latched Latched
NOTES
1. ↑+ = Positive logic transition; ↓– = Negative logic transition; X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all zeros.
3. During power shutdown, reprogramming of any internal registers can take place, but the output amplifiers do not produce the new values until the part is taken out
of shutdown mode.
4. The
LDAC
input is a level-sensitive input that controls the four DAC registers.
Pin No. Mnemonic Description
1 V
OUT
B DAC B Voltage Output.
2 V
OUT
A DAC A Voltage Output.
3 V
SS
Negative Power Supply Input. Specified range of operation 0 V to −5.5 V.
4 V
REF
A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to V
DD
pin or V
SS
pin.
5 V
REF
B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to V
DD
pin or V
SS
pin.
6 GND Ground Pin.
7 LDAC Load DAC Register Strobe. Level sensitive active low. Transfers all input register data to DAC registers.
Asynchronous active low input. See Table 5 for operation.
8 RS Resets Input and DAC Registers to All Zero Codes. Shift register contents unchanged.
9 CS Chip Select. Active low input. Disables shift register loading when high. Transfers serial register data to the input
register when CS returns high. Does not effect LDAC operation.
10 CLK Schmitt Triggered Clock Input. Positive edge clocks data into shift register.
11 SDI Serial Data Input. Input data loads directly into the shift register.
12 V
REF
D DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to V
DD
pin or V
SS
pin.
13 V
REF
C DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to V
DD
pin or V
SS
pin.
14 V
DD
Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%.
15 V
OUT
D DAC D Voltage Output.
16 V
OUT
C DAC C Voltage Output.
AD7398/AD7399
Rev. C | Page 8 of 24
INPUT REGISTERS
AD7398 SERIAL INPUT REGISTER DATA FORMAT
Data is loaded in the MSB first format.
MSB LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SA SD A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE
Bit Position B14 and Bit Position B15 are the SD and SA power shutdown control bits. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set
to Logic 1, the address decoded by Bit B12 and Bit B13 (A0 and A1) determine the DAC channel that is placed in the power shutdown state.
AD7399 SERIAL INPUT REGISTER DATA FORMAT
Data is loaded in the MSB first format.
MSB LSB
B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SA SD A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE
Bit Position B12 and Bit Position B13 are the SD and SA power shutdown control bits. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set
to Logic 1, the address decoded by Bit B10 and Bit B11 (A0 and A1) determine the DAC channel that is placed in the power shutdown state.
Table 6. AD7398/AD7399 Address Decode Control
SA SD A1 A0 DAC Channel Affected
1 X X X All DACs shutdown
0 1 0 0 DAC A shutdown
0 1 0 1 DAC B shutdown
0 1 1 0 DAC C shutdown
0 1 1 1 DAC D shutdown
0 0 0 0 DAC A input register decoded
0 0 0 1 DAC B input register decoded
0 0 1 0 DAC C input register decoded
0 0 1 1 DAC D input register decoded
AD7398/AD7399
Rev. C | Page 9 of 24
TERMINOLOGY
Relative Accuracy (INL)
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Figure 6 illustrates a typical INL vs. code plot.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. Figure 8 illustrates a typical DNL vs.
code plot.
Zero-Scale Error (V
ZSE
)
Zero-scale error is a measure of the output voltage error from
zero voltage when zero code is loaded to the DAC register.
Full-Scale Error (V
FSE
)
Full-scale error is a measure of the output voltage error from
full-scale voltage when full-scale code is loaded to the DAC
register.
Full-Scale Temperature Coefficient (TC
VFS
)
This is a measure of the change in full-scale error with a change
in temperature. It is expressed in ppm/°C or mV/°C.
DAC Glitch Impulse (Q)
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV − s and
is measured when the digital input code is changed by 1 LSB at the
major carry transition (midscale transition). A plot of the glitch
impulse is shown in Figure 15.
Digital Feedthrough (Q
DF
)
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
CS
Power Supply Sensitivity (PSS)
is held high while the CLK and SDI signals are toggled. It is
specified in nV − s, and is measured with a full-scale code change
on the data bus, such as from all 0s to all 1s and vice versa. A
typical plot of digital feedthrough is shown in Figure 16.
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
sensitivity is quoted in terms of % change in output per % change
in V
DD
for full-scale output of the DAC. V
DD
is varied by ±10%.
Reference Feedthrough (V
OUT
/V
REF
)
This is a measure of the feedthrough from the V
REF
input to the
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to V
REF
. Reference feedthrough is expressed in
dB or mV p-p.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

AD7399BRZ

Mfr. #:
Buy AD7399BRZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Quad Serial-Input 10-Bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet