M41T00CAP
Clock operation
3.1 Clock registers
The M41T00CAP has 8 internal registers which contain clock and calibration data. These
registers are memory locations which contain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™ TIMEKEEPER cells). The external copies are
independent of internal functions except that they are updated periodically by the
simultaneous transfer of the incremented internal copy. The system-to-user transfer of
clock data will be halted whenever the address being read is a clock address (00h to 06h).
The update will resume either due to a stop condition or when the pointer increments to
any non-clock address (07h). Clock registers store data in BCD. The calibration register
stores data in binary format. The internal divider (or clock) chain will be reset upon the
completion of a WRITE to any clock address.
3.2 Calibrating the clock
The M41T00CAP is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed ±23 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ±1 minute per month (see Figure 10:
"Crystal acccuracy across temperature"). When the Calibration circuit is properly employed,
accuracy improves to better than ±2 ppm at 25°C. The oscillation rate of crystals changes
with temperature. The M41T00CAP design employs periodic counter correction. The
calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by
256 stage, as shown in Figure 11: "Clock calibration". The number of times pulses which
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the calibration register. Adding
counts speeds the clock up, subtracting counts slows the clock down. The calibration bits
occupy the five lower order bits (D4-D0) in the calibration register 07h. These bits can be
set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1'
indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a
64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second
either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is
loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual
oscillator cycles, that is +4.068 or 2.034 ppm of adjustment per calibration step in the
calibration register (see Figure 11: "Clock calibration"). Assuming that the oscillator is
running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or 5.35 seconds per month which corresponds to a total possible
adjustment range of +5.5 or 2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T00CAP may
require. The first involves setting the clock, letting it run for a month and comparing it to a
known accurate reference and recording deviation over a fixed period of time. Calibration
values, including the number of seconds lost or gained in a given period, can be found in
application note AN934, “TIMEKEEPER
®
calibration.” This allows the designer to give the
end user the ability to calibrate the clock as the environment requires, even if the final
product is packaged in a non-user serviceable enclosure. The designer could provide a
simple utility that accesses the calibration byte. The second approach is better suited to a
manufacturing environment, and involves the use of the FT/OUT pin. The pin will toggle at
512 Hz, when the stop bit (ST, D7 of 00h) is '0,' and the frequency test bit (FT, D6 of 07h)
is '1.' Any deviation from 512 Hz indicates the degree and direction of oscillator frequency
shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a
+20 ppm oscillator frequency error, requiring a 10 (XX001010) to be loaded into the
calibration byte for correction. Note that setting or changing the calibration byte does not
affect the frequency test output frequency. The FT/OUT pin is an open drain output which
DocID014557 Rev 6 13/24
Clock operation
M41T00CAP
requires a pull-up resistor to V
CC
for proper operation. A 500-10 kW resistor is
recommended in order to control the rise time. The FT bit is cleared on power-down.
Figure 10: Crystal acccuracy across temperature
Figure 11: Clock calibration
3.3 Century bit
Bits D7 and D6 of clock register 02h contain the century enable bit (CEB) and the century
bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0'
at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not
toggle.
AI07888
–160
0
10 20
30
40 50 60
70
F
requen
cy (ppm)
T
empera
ture °
C
80–10
–20–30
–40
–100
–120
–140
–40
–60
–80
20
0
–20
= –0.036 ppm/°C
2
± 0.006 ppm/°
C
2
K
F
= K x(
T –T
O
)
2
F
T
O
= 25°
C ± 5°
C
AI00594B
NOR
MAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
14/24 DocID014557 Rev 6
M41T00CAP
Clock operation
3.5 Oscillator fail detection
If the oscillator fail bit (OF) is internally set to '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of
the clock and date data. In the event the OF bit is found to be set to '1' at any time other
than the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately
reset to '0.' This will restart the oscillator. The following conditions can cause the OF bit to
be set:
The first time power is applied (defaults to a '1' on power-up).
The voltage present on V
CC
is insufficient to support oscillation.
The ST bit is set to '1'.
External interference of the crystal.
The OF bit will remain set to '1' until written to logic '0.' The oscillator must have started and
run for at least 4 seconds before attempting to reset the OF bit to '0.'
3.6 Output driver pin
When the FT bit is not set, the FT/OUT pin becomes an output driver that reflects the
contents of D7 of the calibration register. In other words, when D7 (OUT bit) and D6 (FT
bit) of address location 07h are '0's, then the FT/OUT pin will be driven low.
The FT/OUT pin is an open drain which requires an external pull-up resistor.
3.7 Initial power-on default
Upon initial application of power to the device, the OUT and FT bits will be in the '0' state,
and the ST and OF bits will be in the '1' state. All other register bits will initially power on in
random states (see Table 3: "Preferred default values").
Table 3: Preferred default values
Condition ST OUT FT OF
Initial power-up
(1)
1 0 0 1
Subsequent power-up (with battery backup)
(2)
UC UC 0 UC
Notes:
(1)
State of other control bits undefined.
(2)
UC = unchanged
DocID014557 Rev 6 15/24

M41T00CAPPC1

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Real Time Clock Serial real-time clock (RTC) with integral backup battery and crystal
Lifecycle:
New from this manufacturer.
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