M41T00CAPPC1 Datasheet M41T00CAPPC1 | P7-P9

M41T00CAP

Operation

2 Operation

The M41T00CAP clock operates as a slave device on the I

C serial bus. Access is

obtained by implementing a start condition followed by the correct slave address (D0h).

The 8 bytes contained in the device can then be accessed sequentially in the following

order:

1. Seconds register

2. Minutes register

3. Century/hours register

4. Day register

5. Date register

6. Month register

7. Year register

8. Calibration register

The M41T00CAP clock continually monitors V

for an out-of-tolerance condition. Should

fall below V

PFD

, the device terminates an access in progress and resets the device

address counter. Inputs to the device will not be recognized at this time to prevent

erroneous data from being written to the device from a an out-of-tolerance system. Once

falls below the switchover voltage (V

), the device automatically switches over to the

battery and powers down into an ultra-low current mode of operation to prolong battery life.

If V

BAT

is less than V

PFD

, the device power is switched from V

to V

BAT

when V

drops

below V

BAT

. If V

BAT

is greater than V

PFD

, the device power is switched from V

to V

BAT

when V

drops below V

PFD

. Upon power-up, the device switches from battery to V

. When V

rises above V

PFD

, the inputs will be recognized.

For more information on battery storage life refer to application note AN1012.

2.1 Wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a

bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must

be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is high.

• Changes in the data line, while the clock line is high, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.2 Bus not busy

Both data and clock lines remain high.

2.3 Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

2.4 Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

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Operation

M41T00CAP

2.5 Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

2.6 Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low

level put on the bus by the receiver whereas the master generates an extra acknowledge

related clock pulse. A slave receiver which is addressed is obliged to generate an

acknowledge after the reception of each byte that has been clocked out of the master

transmitter. The device that acknowledges has to pull down the SDA line during the

acknowledge clock pulse in such a way that the SDA line is a stable low during the high

period of the acknowledge related clock pulse. Of course, setup and hold times must be

taken into account. A master receiver must signal an end of data to the slave transmitter by

not generating an acknowledge on the last byte that has been clocked out of the slave. In

this case the transmitter must leave the data line high to enable the master to generate the

STOP condition.

Figure 4: Serial bus data transfer sequence

8/24 DocID014557 Rev 6

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION

CHANGE OF

DATAALLOWED

STOP

CONDITION

M41T00CAP

Operation

Figure 5: Acknowledgement sequence

2.7 READ mode

In this mode the master reads the M41T00CAP slave after setting the slave address (see

Figure 7: "READ mode sequence"). Following the WRITE mode control bit (R/W = 0) and

the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next

the START condition and slave address are repeated followed by the READ mode control

bit (R/W = 1). At this point the master transmitter becomes the master receiver. The data

byte which was addressed will be transmitted and the master receiver will send an

acknowledge bit to the slave transmitter. The address pointer is only incremented on

reception of an acknowledge clock. The M41T00CAP slave transmitter will now place the

data byte at address An+1 on the bus, the master receiver reads and acknowledges the

new byte and the address pointer is incremented to “An+2.”

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 06h). The updating will resume upon a stop condition or when the

pointer increments to any non-clock address (07h).

This is true both in READ mode and WRITE mode.

An alternate READ mode may also be implemented whereby the master reads the

M41T00S slave without first writing to the (volatile) address pointer. The first address that is

read is the last one stored in the pointer (see Figure 8: "Alternative READ mode

sequence").

Figure 6: Slave address location

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FR

MASTER

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

1 2 8 9

MSB LSB

AI00602

R/W

SLAVE ADDRESS

START A

0 1 0 0 01 1

MSB

LSB

DocID014557 Rev 6 9/24

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

M41T00CAPPC1

Mfr. #:

Buy M41T00CAPPC1

Manufacturer:

STMicroelectronics

Description:

Real Time Clock Serial real-time clock (RTC) with integral backup battery and crystal

Lifecycle:

New from this manufacturer.

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M41T00CAPPC1