LT3741/LT3741-1
10
37411ff
For more information www.linear.com/LT3741
BLOCK DIAGRAM
+
+
PWM
COMPARATOR
HIGH SIDE
DRIVER
CBOOT
HG
SW
LG
3k
LOW SIDE
DRIVER
R Q
S
g
m
AMP
g
m
= 475µA/V
R
O
= 3.5M
I
OUT
= 40µA
OSCILLATOR
2V REFERENCE
11µA
90k
1.5V
CURRENT
MIRROR
SYNC
RT
13
CTRL1
5
CTRL BUFFER
VOLTAGE
REGULATOR
AMP
g
m
= 850µA/V
SS
6
VC
10
CTRL2
3
V
REF
2
EN/UVLO
V
IN
1
17
V
CC_INT
19
V
IN
20
15
16
18
SENSE
+
12
SYNCRONOUS
CONTROLLER
INTERNAL
REGULATOR
AND
UVLO
100nF
100nF
5.6µF
47µFF
0.1µF
150µF
×2
2.4µH
R
S
5mΩ
V
OUT
10µF
V
IN
SYNC
402k
133k
82.5k
+
8
SENSE
9
FB
7
+
+
10k
1.21V
40.2k
40.2k
3741 F01
Figure 1. Block Diagram, LT3741
(QFN Package)
LT3741/LT3741-1
11
37411ff
For more information www.linear.com/LT3741
(QFN Package)
Figure 2. Block Diagram, LT3741-1
+
+
+
PWM
COMPARATOR
HIGH SIDE
DRIVER
CBOOT
HG
SW
LG
3k
LOW SIDE
DRIVER
ZERO CROSS
COMPARATOR
R Q
S
g
m
AMP
g
m
= 475µA/V
R
O
= 3.5M
I
OUT
= 40µA
OSCILLATOR
2V REFERENCE
11µA
90k
1.5V
CURRENT
MIRROR
SYNC
RT
13
CTRL1
5
CTRL BUFFER
VOLTAGE
REGULATOR
AMP
g
m
= 850µA/V
SS
6
VC
10
CTRL2
3
V
REF
2
EN/UVLO
V
IN
1
17
V
CC_INT
19
V
IN
20
15
16
18
SENSE
+
12
SYNCRONOUS
CONTROLLER
INTERNAL
REGULATOR
AND
UVLO
100nF
100nF
5.6µF
47µFF
0.1µF
150µF
×2
2.4µH
R
S
5mΩ
V
OUT
10µF
V
IN
SYNC
402k
133k
82.5k
+
8
SENSE
9
FB
7
+
+
10k
1.21V
40.2k
40.2k
3741 F01
BLOCK DIAGRAM
LT3741/LT3741-1
12
37411ff
For more information www.linear.com/LT3741
OPERATION
The LT3741 utilizes fixed-frequency, average current
mode control to accurately regulate the inductor current,
independently from the output voltage. This is an ideal solu-
tion for applications requiring a regulated current source.
The control loop will regulate the current in the inductor
at an accuracy of ±6%. Once the output has reached the
regulation voltage determined by the resistor divider from
the output to the FB pin and ground, the inductor current
will be reduced by the voltage regulation loop. In voltage
regulation, the output voltage has an accuracy of ±1.5%.
For additional operation information, refer to the Block
Diagram in Figure 1.
The current control loop has two reference inputs, deter-
mined by the voltage at the analog control pins, CTRL1 and
CTRL2. The lower of the two analog voltages on CTRL1
and CTRL2 determines the regulated output current. The
analog voltage at the CTRL1 pin is buffered and produces
a reference voltage across an internal resistor. The internal
buffer has a 1.5V clamp on the output, limiting the analog
control range of the CTRL1 and CTRL2 pins from 0V to
1.5V corresponding to a 0mV to 51mV range on the
sense resistor, R
S
. The average current-mode control
loop uses the internal reference voltage to regulate the
inductor current, as a voltage drop across the external
sense resistor, R
S
.
A 2V reference voltage is provided on the V
REF
pin to al-
low the use of a resistor voltage divider to the CTRL1 and
CTRL2 pins. The V
REF
pin can supply up to 500μA and is
current limited to 1mA.
The error amplifier for the average current-mode control
loop has a common mode lockout that regulates the induc-
tor current so that the error amplifier is never operated out
of the common mode range. The common mode range is
from 0V to 2V below the V
IN
supply rail.
The overcurrent set point is equal to the regulated current
level set by the CTRL1 pin with an additional 23mV offset
between the SENSE
+
and SENSE
pins. The overcurrent
is limited on a cycle-by-cycle basis; shutting switching
down once the overcurrent level is reached. Overcurrent
is not soft-started.
The regulated output voltage is set with a resistor divider
from the output back to the FB pin. The reference at the
FB pin is 1.21V. If the output voltage level is high enough
to engage the voltage loop, the regulated inductor current
will be reduced to support the load at the output. If the
voltage at the FB pin reaches 1.5V (~25% higher than the
regulation level), an internal overvoltage flag is set, shut-
ting down switching for 13μs.
The EN/UVLO pin functions as a precision shutdown
pin. When the voltage at the EN/UVLO pin is lower than
1.55V, the internal reset flag is asserted and switching is
terminated. Full shutdown occurs at approximately 0.5V
with a quiescent current of less than A in full shutdown.
The EN/UVLO pin has 130mV of built-in hysteresis. In
addition, a 5.5µA current source is connected to this pin
that allows any amount of hysteresis to be added with a
series resistor or resistor divider from V
IN
.
During startup, the SS pin is held low until the internal
reset goes low. Once reset goes low, the capacitor at the
soft-start pin is charged with an 11μA current source.
The internal buffers for the CTRL1 and CTRL2 signals are
limited by the voltage at the soft-start pin, slowly ramping
the regulated inductor current to the current determined
by the voltage at the CTRL1 or CTRL2 pins.
The thermal shutdown is set at 163°C with C hysteresis.
During thermal shutdown, all switching is terminated and
the part is in reset (forcing the SS pin low).
The switching frequency is determined by a resistor at
the RT pin. The RT pin is also limited to 60µA, while not
recommended, this limits the switching frequency to 2MHz
when the RT pin is shorted to ground. The LT3741 may
also be synchronized to an external clock through the use
of the SYNC pin.

LT3741EFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Power Constant Current Constant Voltage, Synchronous Step-Down Controller
Lifecycle:
New from this manufacturer.
Delivery:
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