LT3741/LT3741-1
9
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For more information www.linear.com/LT3741
PIN FUNCTIONS
(QFN/TSSOP)
EN/UVLO (Pin 1/Pin 4): Enable Pin. The EN/UVLO pin
acts as an enable pin and turns on the internal current
bias core and subregulators at 1.55V. The pin does
not have any pull-up or pull-down, requiring a voltage
bias for normal part operation. Full shutdown occurs at
approximately 0.5V.
V
REF
(Pin 2/Pin 5): Buffered 2V reference capable of
0.5mA drive.
CTRL2 (Pin 3/Pin 6): Thermal control input used to reduce
the regulated current level.
GND (Pins 4,11,14, Exposed Pad Pin 21/Pins 2,7,16,
Exposed Pad Pin 21): Ground. The exposed pad must be
soldered to the PCB
CTRL1 (Pin 5/Pin 8): The CTRL1 pin sets the high level
regulated output current and overcurrent. The maximum
input voltage is internally clamped to 1.5V. The overcurrent
set point is equal to the high level regulated current level set
by the CTRL1 pin with an additional 23mV offset between
the SENSE
+
and SENSE
–
pins.
SS (Pin 6/Pin 9): The Soft-Start Pin. Place an external
capacitor to ground to limit the regulated current during
start-up conditions. The soft-start pin has a 11µA charg-
ing current. This pin controls regulated output current
determined by CTRL1.
FB (Pin 7/
Pin 10): Feedback Pin for Voltage Regulation
and Overvoltage Protection. The feedback voltage is 1.21V.
Overvoltage is also sensed through the FB pin. When the
feedback voltage exceeds 1.5V, the overvoltage lockout
prevents switching for 13μs to allow the inductor current
to discharge.
SENSE
+
(Pin 8/Pin 11): SENSE
+
is the inverting input of
the average current mode loop error amplifier. This pin is
connected to the external current sense resistor, R
S
. The
voltage drop between SENSE
+
and SENSE
–
referenced to
the voltage drop across an internal resistor produces the
input voltages to the current regulation loop.
SENSE
–
(Pin 9/Pin 12): SENSE
–
is the non-inverting
input of the average current mode loop error amplifier.
The reference current, based on CTRL1 or CTRL2 flows
out of the pin to the output side of the sense resistor, R
S
.
VC (Pin 10/Pin 13): VC provides the necessary comp-
ensation for the average current loop stability. Typical
compensation values are 20k to 50k for the resistor and
2nF to 5nF for the capacitor.
RT (Pin 12/Pin 14): A resistor to ground sets the switching
frequency between 200kHz and 1MHz. When using the
SYNC function, set the frequency to be 20% lower than
the SYNC pulse frequency. This pin is current limited to
60µA. Do not leave this pin open.
SYNC (Pin 13/Pin 15): Frequency Synchronization Pin.
This pin allows the switching frequency to be synchronized
to an external clock. The R
T
resistor should be chosen to
operate the internal clock at 20% slower than the SYNC
pulse frequency. This pin should be grounded when not
in use. When laying out board, avoid noise coupling to
or from SYNC trace.
HG (Pin 15/Pin 17): HG is the top-FET gate drive signal
that controls the state of the high-side external power
FET. The driver pull-up impedance is 2.3Ω and pull-down
impedance is 1.3Ω.
SW (Pin 16/Pin 18): The SW pin is used internally as the
lower-rail for the floating high-side driver. Externally, this
node connects the two power-FETs and the inductor.
CBOOT (Pin 17/Pin 19): The CBOOT pin provides a float-
ing 5V regulated supply for the high-side FET driver. An
external Schottky diode is required from the V
CC_INT
pin
to the CBOOT pin to charge the CBOOT capacitor when
the switch-pin is near ground.
LG (Pin 18/Pin 20): LG is the bottom-FET gate drive signal
that controls the state of the low-side external power-FET.
The driver pull-up impedance is 2.3Ω and pull-down
impedance is 1.0Ω.
V
CC_INT
(Pin 19/Pin 1): A regulated 5V output for charging
the CBOOT capacitor. V
CC_INT
also provides the power
for the digital and switching subcircuits. Below 6V V
IN
,
tie this pin to the rail. V
CC_INT
is current limited to 50mA.
Shutdown operation disables the output voltage drive.
V
IN
(Pin 20/Pin 3): Input Supply Pin. Must be locally
bypassed with a 4.7μF low-ESR capacitor to ground.
