L6565
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DESCRIPTION
(continued)
Converter's power capability variations with the mains voltage are compensated by line voltage feedforward.
At light load the device features a special function that automatically lowers the operating frequency still main-
taining the operation as close to ZVS as possible. In addition to very low start-up and quiescent currents, this
feature helps keep low the consumption from the mains at light load and be Blue Angel and Energy Star com-
pliant.
The IC includes also a disable function, an on-chip filter on current sense, an error amplifier with a precise ref-
erence voltage for primary regulation and an effective two-level overcurrent protection.
PIN CONNECTION
(Top view, Minidip and SO8)
PIN DESCRIPTION
N° Name Function
1 INV Inverting input of the error amplifier. The information on the output voltage is fed into the pin
through either a resistor divider (primary regulation) or an optocoupler (secondary feedback).
This pin can be grounded in some secondary feedback schemes (see pin 2).
2 COMP Output of the error amplifier. Typically, a compensation network is placed between this pin and
the INV pin to achieve stability and good dynamic performance of the voltage control loop. With
secondary feedback, the pin can be also driven directly by an optocoupler to control PWM by
modulating the current sunk from the pin (with the INV pin grounded).
3 VFF Line voltage feedforward. The information on the converter’s input voltage is fed into the pin
through a resistor divider and is used to change the setpoint of the pulse-by-pulse current
limitation (the higher the voltage, the lower the setpoint). If this function is not desired the pin will
be grounded and the current limitation setpoint will be maximum.
4 CS Input to the PWM comparator. The primary current is sensed through a resistor, the resulting
voltage is applied to this pin and compared with an internal reference to determine MOSFET’s
turn-off. The internal reference is clamped at a value, which defines the pulse-by-pulse current
limitation setpoint, depending on the voltage at pin VFF. If the signal at the pin CS exceeds 2 V,
the gate driver will be disabled (Hiccup-mode OCP).
5 ZCD Transformer’s demagnetization sensing input for Quasi-Resonant operation. Alternately,
synchronization input for an external signal. A negative-going edge triggers MOSFET’s turn-on.
The trigger circuit is blanked for a minimum of 3.5 µs after MOSFET turn-off, for safe operation
under short circuit conditions and frequency foldback. If the pin is grounded the IC will be
disabled.
6 GND Ground. Current return for both the signal part of the IC and the gate driver.
7 GD Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s
with a peak current of 400 mA (source and sink).
8 Vcc Supply Voltage of both the signal part of the IC and the gate driver. An electrolytic capacitor is
connected between this pin and ground. A resistor connected from this pin to the converter’s
input bulk capacitor will be typically used to start up the device.
ZCD
INV
COMP
VFF
CS
Vcc
GD
GND
1
2
3
4
8
7
6
5
