7/17
L6565
APPLICATION INFORMATION
Quasi-resonant operation in offline flyback converters lies in synchronizing MOSFET's turn-on to the transform-
er's demagnetization. Detecting the resulting negative-going edge of the voltage across any winding of the
transformer can do this. The L6565 is provided with a dedicated pin that allows doing the job with a very simple
interface, just one resistor.
Variable frequency operation - as a result of different operating conditions in terms of input voltage and output
current - is inherent in such functionality. The system always works close to the boundary between DCM (Dis-
continuous Conduction Mode) and CCM (Continuous Conduction Mode) operation of the transformer. The op-
eration is then identical to that of the so-called self-oscillating or Ringing Choke Converter (RCC).
Detailed Device Description
Internal Supply Block (see fig. 12)
A linear voltage regulator supplied by V
cc
(pin 8) generates an internal 7V rail used for supplying the entire IC,
except for the gate driver that is supplied directly from Vcc. In addition, a bandgap circuit generates a precise
internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation with primary feed-
back technique.
In figure 12 it is also shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the
chip as long as the Vcc voltage is high enough to ensure a reliable operation.
Figure 12. L6565 internal supply block
+Vin
REF.
UVLO
-
+
8
2.5V
7V bus
LIN.
REG.
Vcc
L6565
8/17
Zero Current Detection and Triggering Block (see fig. 13):
The Zero Current Detection (ZCD) block switches on the external MOSFET if a negative-going edge falling be-
low 1.6 V is applied to the input (pin 5, ZCD). However, to ensure high noise immunity, the triggering block must
be armed first: prior to falling below 1.6V, the voltage on pin 5 must experience a positive-going edge exceeding
2.1 V.
This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the
ZCD input is obtained from the transformer's auxiliary winding used also to supply the IC. Alternatively, this can
be used to synchronize MOSFET's turn-on to the negative-going edge of an external clock signal, in case the
device is not required to work in QR mode but as a standard PWM controller in a synchronized system (e.g.
monitor SMPS).
The triggering block is blanked for a certain time after the MOSFET has been turned off. This has two goals:
first, to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the
ZCD circuit erroneously; second, to realize the Frequency Foldback function (see the relevant description).
Figure 13. Zero Current Detection and Triggering Block; Disable and Frequency Foldback Blocks
A circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD pin.
This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the MOSFET.
To minimize the external interface with the synchronization source (either the auxiliary winding or an external
clock), the voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal dia-
gram of the ZCD block of figure 13. The upper clamp is typically located at 5.2 V, while the lower clamp is at
one V
BE
above ground. The interface will then be made by just one resistor that has to limit the current sourced
by and sunk from the pin within the rated capability of the internal clamps.
Disable Block (see fig. 13):
The ZCD pin is used also to activate the Disable Block. If the voltage on the pin is taken below 150 mV the de-
vice will be shut down. To do so, it is necessary to override the source capability (10 mA max.) of the internal
lower clamp. While in disable, the current consumption of the IC will be reduced. To re-enable device operation,
the pull-down on the pin must be released.
Frequency Foldback Block (see fig. 13):
To prevent the switching frequency from reaching too high values, which is a typical drawback of QR operation,
1.6V
2.1V
0.2V
0.3V
DISABLE
5
GD
DRIVER
+
-
5.2V
+Vin
ZCD
PWM
7
150µA
R
S
Q
BLANKING
TIME
+
-
2.5V
INVCOMP
E/A
Q
to line
FFWD
L6565
STARTER
+
-
MONO
STABLE
R
ZCD
starter STOP
blanking
START
9/17
L6565
the L6565 puts a limit on the minimum OFF-time of the switch. This is done by blanking the triggering block of
the ZCD circuit as mentioned before. The duration of the blanking time (3.5µs min.) is a function of the error
amplifier output VCOMP, as shown in the diagram of figure 6.
If the load current and the input voltage are such that the switch OFF-time falls below the minimum blanking
time of 3.5µs, the system will enter the "Frequency Foldback" mode, a sort of "ringing cycle skipping" illustrated
schematically in figure 14.
Figure 14. Frequency foldback: ringing cycle skipping as the load is progressively reduced
In this mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that
the OFF-time of the MOSFET is allowed to change with discrete steps (2·Tv), while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compen-
sated by one or more shorter ones and vice versa. However, this mechanism is absolutely normal and there is
no appreciable effect on the performance of the converter or on its output voltage.
t
V
DS
TFW
T
BLANKmin
TV
t
V
DS
T
BLANK
Pin = Pin'
(limit condition)
Pin = Pin'' < Pin' Pin = Pin''' < Pin''
t
V
DS
T
BLANK
Figure 15. Frequency Foldback: qualitative
frequency dependence on power
throughput
Further load reductions involve lower values for
VCOMP, which increases the blanking time. There-
fore, more and more ringing cycles will be skipped.
When the load is low enough, so many ringing cycles
need to be skipped that their amplitude becomes
very small and they can no longer trigger the ZCD cir-
cuit. In that case the internal starter of the IC will be
activated, resulting in burst-mode operation: a series
of few switching cycles spaced out by long periods
where the MOSFET is in OFF state.
Voltage Feedforward block (see fig. 17b):
The power that QR flyback converters with a fixed
overcurrent setpoint (like fixed-frequency systems)
are able to deliver changes with the input voltage
considerably. With wide-range mains, at maximum
line it can be more than twice the value at minimum
line, as shown by the upper curve in the diagram of
figure 16. The L6565 has the Line Feedforward func-
tion available to solve this issue.
Figure 16. Typical power capability change vs.
input voltage in ZVS QR flyback
converters
f
sw
Pin
BURST MODE
without frequency foldback
with frequency foldback
Vin fixed
Vin
Vinmin
P
inlim
@ V
in
Pinlim @ Vinmin
11.522.533.54
0.5
1
1.5
2
2.5
system optimally
compensated
system not
compensated

L6565DTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Switching Controllers Current-Mode Pri Cnt
Lifecycle:
New from this manufacturer.
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