L6565
4/17
G
V
Voltage Gain Open loop 60 80 dB
GB Gain-Bandwidth Product 1 MHz
I
COMP
Source Current V
COMP
= 4V, V
INV
= 2.4 V -2 -3.5 -5 mA
Sink Current V
COMP
= 4V, V
INV
= 2.6 V 2.5 4.5 mA
V
COMP
Upper Clamp Voltage I
SOURCE
= 0.5 mA 5 5.5 V
Lower Clamp Voltage I
SINK
= 0.5 mA 2.25 2.55 V
CURRENT SENSE COMPARATOR
I
CS
Input Bias Current V
CS
= 0 -0.05 -1 µA
t
d(H-L)
Delay to Output 200 450 ns
V
CSx
Current Sense Reference Clamp
V
COMP
= Upper clamp, V
VFF
= 0V
1.28 1.4 1.5 V
V
COMP
= Upper clamp, V
VFF
= 1.5V
0.62 0.7 0.78
V
COMP
= Upper clamp, V
VFF
= 3V
00.2
V
CSdis
Hiccup-mode OCP level 1.85 2.0 2.2 V
ZERO CURRENT DETECTOR/ SYNCHRONIZATION
V
ZCDH
Upper Clamp Voltage I
ZCD
= 3mA 4.7 5.2 6.1 V
V
ZCDL
Lower Clamp Voltage I
ZCD
= - 3mA 0.3 0.65 1 V
V
ZCDA
Arming Voltage
(positive-going edge)
(1)
2.1 V
V
ZCDT
Triggering Voltage
(negative-going edge)
1.6 V
I
ZCDb
Input Bias Current V
ZCD
= 1 to 4.5 V 2 µA
I
ZCDsrc
Source Current Capability -3 -10 mA
I
ZCDsnk
Sink Current Capability 3 10 mA
V
DIS
Disable Threshold 150 200 250 mV
I
ZCDr
Restart Current After Disable V
ZCD
< V
DIS
, Vcc > Vcc
off
-70 -150 -230 µA
T
BLANK
Blanking time after pin 7 high-to-
low transition
V
COMP
≥ 3.2 V 3.5 µs
V
COMP
= 2.5 V 18
START TIMER
t
START
Start Timer period 250 400 550 µs
GATE DRIVER
V
OL
Dropout Voltage I
GDsource
= 200mA 1.2 2 V
I
GDsource
= 20mA 0.7 1
V
OH
I
GDsink
= 200mA 2 V
I
GDsink
= 20mA 0.3
t
f
Current Fall Time 40 100 ns
t
r
Current Rise Time 40 100 ns
I
GDoff
I
GD
sink current Vcc = 4 V, V
GD
= 1 V 5 10 mA
(1) Parameters guaranteed by design, not tested in production.
ELECTRICAL CHARACTERISTCS
(continued)
(T
j
= -25 to 125°C, V
CC
= 12V, C
o
= 1nF; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
