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MJE5851G

P1-P3P4-P6P7-P8
MJE5850, MJE5851, MJE5852
www.onsemi.com
4
1
IN
PUT
R
coil
L
coil
V
CC
V
clamp
RS =
0.1 W
1N4937
OR
EQUIVALENT
TUT
SEE ABOVE FOR
DETAILED CONDITIONS
20
1
0
PW Varied to Attain
I
C
= 100 mA
2
-10 V
t
1
I
CM
t
f
Clamped
t
f
t
t
V
clamp
t
2
TIM
E
V
CEM
1
2
TUT
R
L
V
CC
t
1
Adjusted to
Obtain I
C
Test Equipment
Scope — Tektronix
475 or Equivalent
t
1
≈
L
coil
(I
CM
)
V
CC
t
2
≈
L
coil
(I
CM
)
V
Clamp
V
CEO(sus)
RBSOA AND INDUCTIVE SWITCHING RESISTIVE SWITCHING
INPUT
CONDITIONS
CIRCUIT
VALUES
TEST CIRCUITS
−V adjusted to obtain desired I
B1
+V adjusted to obtain desired V
BE(off)
+ V
50 W
2 W
INPUT
0
0.2 mF
0.0025 mF
0.1 mF
500 W
1/2 W
500 W
0.0033 mF
500 W
1/2 W
+ V
50 mF
0.1 mF
MJE15029
1
2
1 W 2
W
MJE15028
50 mF
- V
+-
1/2 W
1N4934
0.1 mF
-+
500 W
1/2 W
0.2 mF
I
B1
adjusted to
obtain the forced
h
FE
desired
TURN−OFF TIME
Use inductive switching
driver as the input to
the resistive test circuit.
I
B1
1
2
TURN−ON TIME
L
coil
= 80 mH, V
CC
= 10 V
R
coil
= 0.7 W
L
coil
= 180 mH
R
coil
= 0.05 W
V
CC
= 20 V
V
CC
= 250 V
R
L
= 62 W
Pulse Width = 10
ms
INDUCTIVE TEST CIRCUIT RESISTIVE TEST CIRCUITOUTPUT WAVEFORMS
V
clamp
= 250 V
R
B
adjusted to attain desired I
B1
V
CE
I
C
Table 1. TEST CONDITIONS FOR DYNAMIC PERFORMANCE
, CROSSOVER TIME (t
c
μs)
t
ti
Figure 7. Inductive Switching Measurements
TIME
I
B
V
CE
90% I
B1
t
sr
t
c
10%
V
CEM
Figure 8. Inductive Switching Times
I
C
= 4 A
I
C
/I
B
= 4
T
J
= 25°C
t
c
100°C
t
sv
100°C
t
sv
25°C
t
c
25°C
V
BE
, BASE-EMITTER VOLTAGE (VOLTS)
0
0.4
0.2
1.0
0.6
0.8
368057214
t
sv
, VOLTAGE STORAGE TIME (μs)
0
0.9
0.3
2.7
1.5
2.1
1.2
0.6
3.0
1.8
2.4
I
C
10%
I
CM
2%
I
CM
t
rv
t
fi
90%
I
CM
I
CM
V
CEM
V
clamp
MJE5850, MJE5851, MJE5852
www.onsemi.com
5
SWITCHING TIMES NOTE
In resistive switching circuits, rise, fall, and storage times
have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage
waveforms are not in phase. Therefore, separate
measurements must be made on each waveform to
determine the total switching time. For this reason, the
following new terms have been defined.
t
sv
= Voltage Storage Time, 90% I
B1
to 10% V
CEM
t
rv
= Voltage Rise Time, 10−90% V
CEM
t
fi
= Current Fall Time, 90−10% I
CM
t
ti
= Current Tail, 10−2% I
CM
t
c
= Crossover Time,10% V
CEM
to 10% I
CM
An enlarged portion of the inductive switching waveform
is shown in Figure 7 to aid on the visual identity of these
terms.
For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained
using the standard equation from AN−222A:
P
SWT
= 1/2 V
CC
I
C
(t
c
)f
In general, t
rv
+ t
fi
] t
c
. However, at lower test currents
this relationship may not be valid.
As is common with most switching transistors, resistive
switching is specified at 25°C and has become a benchmark
for designers. However, for designers of high frequency
converter circuits, the user oriented specifications which
make this a “SWITCHMODE” transistor are the inductive
switching speeds (t
c
and t
sv
) which are guaranteed at 100_C.
t, TIME (s)μ
t, TIME (ms)
1
0.01
0.01
0.7
0.2
0.1
0.05
0.02
r(t), TRANSIENT THERMAL RESISTANCE
0.05 1 2 5 10 20 50 100 200 500
Z
q
JC(t)
= r(t) R
q
JC
R
q
JC
= 1.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
Z
q
JC(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
D = 0.5
0.2
0.01
SINGLE PULSE
0.1
0.1 0.50.2
(NORMALIZED)
1 k
0.5
0.3
0.07
0.03
0.02
I
C
, COLLECTOR CURRENT (AMPS)
t
r
Figure 9. Turn−On Switching Times Figure 10. Turn−Off Switching Time
0.1
0.3
0.2
10
0.4
Figure 11. Typical Thermal Response [Z
q
JC
(t)]
0.02
0.01
1.0
0.7
0.3
0.2
0.5
0.1
I
C
, COLLECTOR CURRENT (AMPS)
0.7 3.0 102.0 5.00.1 1.0 7.0
V
CC
= 250 V
I
C
/I
B
= 4
T
J
= 25°C
0.5
0.03
0.05
0.07
0.7
V
CC
= 250 V
I
C
/I
B
= 4
V
BE(off)
= 5 V
T
J
= 25°C
0.30.2
0.7 4.0 100.1 2.0 7.00.50.3 1.0
t, TIME (s)μ
t
d
t
s
t
f
0.02
0.05
MJE5850, MJE5851, MJE5852
www.onsemi.com
6
The Safe Operating Area figures shown in Figures 12 and 13 are
specified for these devices under the test conditions shown.
I
C
, COLLECTOR CURRENT (AMPS) I
C
, COLLECTOR CURRENT (AMPS)
7.0
0
1.0
100 300 500
3.0
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
5.0
5 ms
100 ms
dc
20
7.0
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
0.05
10 400
5.0
2.0
10
1.0
0.2
0.1
BONDING WIRE LIMIT
THERMAL LIMIT
(SINGLE PULSE)
SECOND BREAKDOWN LIMIT
20 40 70 100
Figure 12. Maximum Forward Bias
Safe Operating Area
T
C
=
25°C
Figure 13. RBSOA, Maximum Reverse Bias
Safe Operating Area
0.5
0.02
300
200 400
500
I
C
/I
B
= 4
V
BE(off)
= 2 V to 8 V
T
J
= 100°C
MJE5850
MJE5851
MJE5852
8.0
2.0
4.0
6.0
MJE5850
MJE5851
MJE5852
200
1 ms
Safe Operating Area Information
Forward Bias
There are two limitations on the power handling ability of
a transistor average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation, i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 12 is based on T
C
= 25_C; T
J(pk)
is
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when T
C
≥ 25_C. Second breakdown limitations do
not derate the same as thermal limitations. Allowable
current at the voltages shown on Figure 12 may be found at
any case temperature by using the appropriate curve on
Figure 15.
T
J(pk)
may be calculated from the data in Figure 11. At
high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations
imposed by second breakdown.
Reverse Bias
For inductive loads, high voltage and high current must be
sustained simultaneously during turn−off, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage−current condition allowable
during reverse biased turn−off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 13 gives the RBSOA
characteristics.
Figure 14. Peak Reverse Base Current Figure 15. Forward Bias Power Derating
I
C
= 4 A
I
B1
= 1 A
T
J
= 25°C
T
C
, CASE TEMPERATURE (°C)
0
40 120 160
0.6
POWER DERATING FACTOR
SECOND BREAKDOWN
DERATING
1
0.8
0.4
0.2
60 100 14080
THERMAL
DERATING
200
1.0
268
2.5
3.5
3.0
2.0
1.5
4
V
BE(off)
, BASE-EMITTER VOLTAGE (VOLTS)
I
B2(pk)
(AMPS)
P1-P3P4-P6P7-P8

MJE5851G

Mfr. #:
Buy MJE5851G
Manufacturer:
ON Semiconductor
Description:
Bipolar Transistors - BJT 8A 350V 80W PNP
Lifecycle:
New from this manufacturer.
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