XRD98L61
20
Rev. 2.00
ANALOG TO DIGITAL CONVERTER (ADC)
The analog-to-digital converter is based on pipeline
architecture with a built in track & hold input stage. The
track & hold and ADC conversion are controlled by the
externally supplied ADCLK.
The polarity of the ADCLK is programmable. If ADCpol
= low, the track & hold circuit tracks the PGA output
while ADCLK is high and holds while ADCLK is low. If
ADCpol = high, the track & hold circuit tracks the PGA
output while ADCLK is low and holds while ADCLK is
high. ADCLK should be a 50% duty cycle clock, and
should be synchronized with SBLK such that ADC
tracking ends at the same time as the CDS sample
black ends. (See Figure 13).
The ADC reference levels, CapP & CapN, are gener-
ated from an internal voltage reference. To minimize
noise, these pins should have high frequency bypass
capacitors to AGND. The value of these bypass ca-
pacitors will affect the time required for the reference
to charge up and settle after power down mode.
The ADC output bus, DB[11:0] & OVER, has 3-state
capability that is controlled by the OE bit of the Control
register. The outputs are enabled when the OE bit is
high. The outputs are high impedance when the OE bit
is low.
Direct ADC Input Mode
The ADC inputs can be accessed directly via the
ADCinP & ADCinN pins. To enable the Direct ADC
Input mode, write a “1” to the ADCtest bit of the Control
register. This will disable the CDS/PGS and connect
the ADCinP & ADCinN pins directly to the ADC. The
ADC data is valid 6.5 clock cycles after the sampling
edge of ADCLK (default is falling edge).
POWER DOWN
The Power Down mode can be activated by forcing the
PD pin high, or by writing a “1” to the PwrDwn bit in the
Control register. For normal operation, the PD pin
must be low and the PwrDwn bit must be “0”. In the
Power Down mode, all analog circuits are turned off,
the calibration is placed in the Hold mode, and the
output bus, (DB[11:0] and OVER) is put in the high
impedance mode. All the digital registers retain their
values, so the PGA gain, offset, and calibration will
return to their previous states. The serial interface pins
remain active in the Power Down mode. The PD pin
and the PwrDwn bit do not reset any internal registers.
In addition to the PwrDwn bit, there are 4 other power
down bits which only turn off portions of the chip.
DAC1pd and DAC0pd control the two 8 bit utility
DACs. AFEpd controls the CDS & PGA circuits.
ADCpd controls the ADC. AFEpd & ADCpd are in-
cluded for factory test and characterization purposes;
they are not intended for use in digital camera applica-
tions.
DIGITAL OUTPUT ENABLE CONTROL
The digital output bus, DB[11:0] and OVER, has 3-
state capability. When the OE bit in the control register
is high, and the OE Pin (#24) is high, the digital output
drivers are enabled and active. When the OE bit is low,
or the OE Pin is low, the digital output drivers are
disabled and the bus is in the high impedance state.
The OE bit and OE Pin only control the digital output
drivers; all other circuits on the chip will remain active.
The black level calibration can still run properly when
the outputs are in the high impedance state.
CHIP RESET
The chip includes a Power-On-Reset function (POR),
so when the power supplies are turned on, the chip will
always power up with default values in all registers.
There are two methods to force a chip reset. The first
is to write a “1” to the RESET bit in the reset register.
This will reset the chip, and after a delay of about 10 ns,
the reset bit will automatically clear itself. The second
reset method is to force the RESET pin high. This will
reset the chip until the RESET pin goes low again. The
RESET pin has an internal pull down.
